在射頻積體電路(RFIC)中，收發器(Transceiver)的鎖相迴路(Phase Locked Loop)的特性非常重要，而PLL內部包含有相位偵測器(PFD)、充電幫浦(CP)、迴路濾波器(LF)、壓控振盪器(VCO)、除頻器(FD)、倍頻器(FM)。在追求低消耗功率、低相位雜訊(Phase Noice)以及較寬的除頻範圍之下，又以壓控振盪器和注入鎖定除頻器的性能最為重要。在此特別研究鎖相迴路中的注入鎖定除頻器及倍頻器。
在本篇論文中提出了使用八字電感來降低磁耦合的雙頻帶除二注入鎖定除頻器及兩顆使用不同方式設計的倍頻器。首先，第一顆晶片使用台積電(TSMC) 0.18 um 製程來完成具有低磁耦合的雙頻帶除二注入除頻器。這顆除頻器以相反磁通量之八字電感與兩組交叉偶合(cross couple)並聯作為主要核心，並結合單一注入的MOSFET來達到除二的效果。晶片面積為716 x 774.052 mm2。在驅動電壓為0.65V時，其功耗為4.72mW。在0 dbm的注入訊號強度之下，除頻比例為82.9%，從注入4.28 GHz到10.41 GHz範圍共6.13 GHz。
其次，第二顆晶片使用台積電(TSMC) SiGe 0.35 um製程實現注入雙推式放大器倍頻器。這顆倍頻器使用了共用電流(Current-Reused)來降低功耗並且以HBT架構作堆疊。整個晶片面積為0.698x0.803 mm2。驅動電壓為0.2 V時，其功耗為5.34 mW。在輸入功率Pinj = 0 dbm的情形下，可工作範圍為2.98 GHz～3.8 GHz。
最後一顆晶片使用台積電(TSMC) 0.18 um 製程來實現低功耗D類震盪器倍頻器。這顆倍頻器使用一組LC諧振器和一組電容交叉耦合MOSFET對。整個晶片面積為1x1 mm2。在驅動電壓為0.4V時，其功耗為2.16 mW，其倍頻F.O.M為-174.23 dBc/Hz。

In RFIC, the characteristics of Phase Locked Loop of Transceiver are very important. The PLL contains Phase Frequency Detector (PFD), Charge Pump (CP), Loop Filter (LF), Voltage Controlled Oscillator (VCO), and Frequency Divider (FD). In pursuit of low power consumption, low Phase Noice, and a wide range of frequency division, the performance of the Voltage Controlled Oscillator and the Injection-Locked Frequency Divider is important. The Injection-Locked Frequency Divider in the Phase-Locked Loop is studied.
In this thesis, we propose the Dual band divide-by-2 ILFD, using an 8-Shaped inductor to reduce magnetic coupling, and two different kinds of frequency multipliers are designed.
First of all, in the process of the TSMC 0.18 um, the Dual-band divide-by-2 ILFD is proposed by using 8-Shaped inductor to lower magnetic coupling. Using the 8-Shaped inductor with opposite magnetic flux and two sets of cross couples connected in parallel as the main core, the Dual band divide-by-2 ILFD is combined with a single-injected MOSFET to achieve the effect. The size of chip is 716 x 774.052 mm2. The power supply voltage is 0.65V, the power consumption is 4.72mW and the locking range is 6.13 GHz, from 4.28 GHz to 10.41 GHz (82.9%) at injection power of Pinj = 0 dbm.
Secondly, we propose a low power Frequency Doubler (FD) in the process of TSMC 0.35 µm BiCMOS. In the structure of HBT, the FD reduces the power by using Current-Reused. The size of the chip is 0.698 × 0.803 mm2. At the power consumption of 5.34 mW and the input power of Pinj=0 dBm, the operation range is from 2.98 GHz to 3.8 GHz.
Finally, we design a low power class-D Oscillator Frequency Doubler in the process of TSMC 0.18 μm BiCMOS. The size of the chip is 1×1 mm2. At the supply voltage of 0.4 V, the power consumption is 2.16 mW, and the output of doubler F.O.M is -174.23 dBc/Hz. This class-D Oscillator Frequency Doubler is made of a LC resonator and a capacitive cross-coupled MOSFET pairs.

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