本論文主要研究在多層板的電路設計中如何減少電壓調節模組切換雜訊的影響。切換式VRM為了提供穩定的電流會頻繁地切換其工作狀態。然而，在其切換過程中,它會產生變化的電壓（dv/dt）與變化的電流（dI/dt），這些會對我們的訊號完整性與電源完整性造成影響。本論文會根據實際多層印刷電路板的情況採用背鑽的方式來減少電壓調節模組切換雜訊，並在頻域與時域上展現成果。模擬的成果會提供有價值的多層印刷電路板佈局規則去參考。

This thesis mainly discusses that how to reduce voltage regulator module(VRM) switching noise in multi-layer circuit design. The switching VRM quickly changes its working state to provide steady current on loadings. However, it causes changing voltage(dv/dt) and changing current(dI/dt) because of its fast changing, which brings signal integrity (SI) and power integrity (PI) problems. This thesis will use backdrill to reduce VRM switching noise according to the reality multi-layer printed circuit board layout and show the result both in time domain and frequency domain. The simulation result will provide valuable multi-layer circuit layout rules to refer to.

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