本論文研究積體電路晶片間的光互連與對準技術，利用CIC之CMOS製程來設計積體電路。文中探討四個主題，矽發光晶片、矽光二極體、限幅放大器與積體電路晶片間的光互連與對準。
第一部分探討矽發光元件的研製，採用指叉式結構來研究矽發光晶片的發光特性，設計的P-N接面矽發光晶片，在面積500 × 80 µm2下，所得外部量子效率為1.298×10-6 。
第二部分為矽光二極體（Si-Photo Diode）的設計，所得PNNNP型矽光二極體之最高反應率R＝0.21（A/W）與量子效率 ＝0.4，NPPPN型矽光二極體之最高反應率R＝0.198（A/W）與量子效率 ＝0.378。
第三部份為限幅放大器設計，量測所得放大率為40.83dB，-3dB頻寛約為3MHz。
第四部分為積體電路矽晶片間對準技術之研究，晶片間橫向對準的精密度可達1µm，垂直最遠距離可達10mm以內，量測得矽發光晶片之最大光功率約45nW且光發散角為θ＝46.990。
以上四個主題，相同的特色就是皆採用矽為材料，利用CMOS製程可供發展光電積體電路(OEIC)的應用。

In this thesis, a study of the chip-to-chip optical interconnect and chip-to-chip alignment technique is presented. CMOS process provided by CIC (Chip Implement Center) is used. Here, we study four topics: the silicon light emission, the silicon photodiode, the limiting amplifier and the study of the chip-to-chip optical interconnect and alignment technique.
The first part deals with the CMOS silicon light-emitting chip. Finger structures are used to study the efficiency of light emission. Silicon light emission chips of pn junctions are designed. The maximum quantum external efficiency obtained is 1.298×10-6 with an area of 500×80 µm2.
The second part is about the silicon photodiode chip, The PNNNP type has a maximum responsivity R=0.21(A/W) and a quantum efficiency =0.4. The NPPPN type has a maximum responsivity R=0.198(A/W) and a quantum efficiency =0.378 in our work.
The third part is about the limiting amplifier. The amplifier we designed has 40.83dB gain and 3MHz bandwidth.
In the last, the chip-to-chip optical alignment technique is presented. The horizontal resolution can reach 1µm in our movable stage and the farthermost vertical distance reaches 10mm. Besides, the maximum light intensity is 45nW and the divergence angle is θ=46.990 in our silicon light-emission chip.
In the topics mentioned above, they have the same feature in the use of material, and it can be applied to realize the opto-electronic interconnect among integrated circuit chips.

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