光網路晶片已成為一個未來的趨勢，相較於傳統的晶片，在晶片上的溝通以及多核的系統中，它提供了更佳的頻寬、更有效率的功耗，和更短的延遲。
作為一個光網路晶片的重要元件，光繞線器由波導和光敏開關 (Photonic switching element) 所構成，並於兩個樞紐或一個樞紐及一個記憶體控制器間做繞線。許多先前的研究都著重於發展一個有效率的架構，然而在物理的實作上卻有可能導致一個好的架構效率低落，但這卻鮮少有人研究。
現存的自動擺置與繞線工具面臨了雷射能量損失的問題，而這些能耗主要來自於光敏開關外波導的交叉。藉由觀察這些架構，我們發現了其實大部分的架構都是平面的，我們使用這個特性發展了一個同時擺置與繞線的系統名為PlanarONoC，其可以保證波導交叉的最小化。
實驗結果顯示我們的方法相較於現有最新的技術可以更有效率，並平均降低能耗達百分之三十七，且保證沒有任何光敏開關外的波導交叉。

Optical networks-on-chips (ONoCs) have become a promising solution for the
on-chip communication of multi-and many-core systems to provide superior communication bandwidths, efficiency in power consumption, and latency performance
compared to electronic NoCs. Serving as the critical part of ONoCs, an optical
router composed of waveguides and photonic switching elements (PSEs) routes signals between two hubs or between a hub and a memory controller. Many studies focus on developing efficient architectures of optical routers, while their physical implementation that can seriously deteriorate the quality of the architectures is rarely addressed. The existing automatic place-and-route tools suffer from considerable insertion loss due to many waveguide crossings outside of PSEs, which leads to huge power consumption of laser sources. By observing that the logic schemes of most optical routers are actually planar, we develop a concurrent PSE placement and waveguide routing flow, called PlanarONoC, that guarantees optimal solutions in terms of crossings for planar logic schemes. Experimental results show that the proposed flow reduces the maximum insertion loss by 37% on average, guarantees no waveguide crossing outside of PSEs, and performs much more efficient compared to the state-of-the-art work.

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