簡易檢索 / 詳目顯示

研究生: 廖麗鳳
Li-Feng Liao
論文名稱: 溝渠式絕緣閘極雙極性電晶體之結構設計
Structure Design of Trench Type Insulated-Gate Bipolar Transistors
指導教授: 莊敏宏
Miin-Horng Juang
口試委員: 張勝良
Sheng-Lyang Jang
徐世祥
Shih-Hsiang Hsu
學位類別: 碩士
Master
系所名稱: 電資學院 - 電子工程系
Department of Electronic and Computer Engineering
論文出版年: 2014
畢業學年度: 102
語文別: 英文
論文頁數: 69
中文關鍵詞: 功率元件溝渠式絕緣閘極穿隧型場效電晶體絕緣閘極雙極性電晶體閂鎖效應
外文關鍵詞: power device, trench-gate, IGBT, TFET, latch-up
相關次數: 點閱:481下載:11
分享至:
查詢本校圖書館目錄 查詢臺灣博碩士論文知識加值系統 勘誤回報

本論文主要研究功率半導體元件,而做為開關器使用之功率半導體元件,理想上的導通狀態為短路,並且在截止狀態為開路;在市面上像是傳統的功率金屬氧化物半導體場效電晶體(MOSFET)在耐高電壓時有過大的串聯電阻的問題,而另一種元件-絕緣閘極雙極性電晶體(IGBT)雖解決前者的串聯電阻過大之問題,可是因為元件本身有寄生的閘流體結構,易造成元件發生閂鎖效應,造成閘極失去控制能力,嚴重時易使元件燒掉,所以,本論文提出一新型溝渠式垂直結構之絕緣閘極雙極性元件,不只可以改善串聯電阻過大問題,且藉由穿隧型場效電晶體結構取代傳統絕緣閘極雙極性電晶體內的金屬氧化物半導體結構觸發產生電流,此新型結構因本身沒有閘流體結構,故可有效避免發生閂鎖問題。

本論文也同時藉由觀察能帶變化探討溝渠式閘極深度與寬度對此元件的影響,像是,觸發穿隧機制的影響或是帶動漂移電場的影響,而除了元件設計,本論文也利用調變不同製程方式調整控制高濃度分佈之區域,使元件可以提高其穿隧效率,進而使元件達到最佳的導通特性。

在最後探討元件的橫向尺寸微縮化時的影響,微縮化元件不只可以提高其崩潰電壓,更可以在每單位面積獲得更佳的導通特性。


Power devices act as a switch to control the power delivered to the load. In this thesis, a novel trench-type insulated-gate bipolar transistor device has been proposed without p-n-p-n latch-up phenomenon, which shows better characteristics as compared with the conventional trench-gate power MOSFET.

Moreover, by using the design of device structure and/or fabrication process to enhance the band-to-band tunneling or increase the electric field in drift region, the on-current of the trench-gate TFET-IGBT can be effectively improved. Accordingly, proper p+ source implantation profile and trench-gate dimension can be employed to optimize the electrical characteristics.

As a result, the trench-gate TFET-IGBT is capable of causing smaller on-resistance than the conventional trench-gate power MOSFET, with avoiding the latch-up problem in the conventional trench-gate MOSFET-IGBT.

摘要 i Abstract ii Acknowledgements iii Contents iv Figure captions vi Chapter 1 Introduction 1 1-1 Device application 1 1-2 Power MOSFETs 3 1-2-1 The operation mechanism of power UMOSFET 4 1-3 Insulated-Gate Bipolar Transistors (IGBT) 6 1-3-1 The operation mechanism of IGBT 7 1-4 Tunneling Field Effect Transistors (TFET) 9 1-4-1 The operation mechanism of power TFET 11 1-5 Motivation 13 1-6 Thesis organization 14 Chapter 2 Device structure and Fabrication 15 2-1 The conventional trench-gate power MOSFET 15 2-2 The conventional trench-gate TFET 21 2-3 The trench-gate TFET-IGBT 27 Chapter 3 Result and Discussion 33 3-1 The electrical characteristics of power MOSFET, TFET, and TFET-IGBT 33 3-1-1 The off-sate I-V characteristics for MOSFET, TFET, and TFET-IGBT 34 3-1-2 The on-sate I-V characteristics for MOSFET, TFET, and TFET-IGBT 35 3-2 The electrical characteristics of TFET-IGBT with various trench-gate depth 37 3-2-1 The I-V characteristics of TFET-IGBT 38 3-3 The electrical characteristics of TFET-IGBT without p-well 42 3-3-1 The I-V characteristics of TFET-IGBT without P- well 43 3-3-2 The I-V characteristics of various trench-gate depth device 45 3-3-3 The I-V characteristics of various trench-gate width device 47 3-3-4 The I-V characteristics of scaling down the lateral pitch size of the device 50 3-4 The electrical characteristics for TFET-IGBT with fabrication modulated of p+ implantation 53 3-4-1 The I-V characteristics of various thermal cycle temperature 56 3-4-2 The I-V characteristics of various trench-gate depth device 57 3-5 Summary 58 Chapter 4 Conclusions 59 Reference 60

Reference
[1] B. J. Baliga, “Power Semiconductor Devices, Boston”, MA: PWS, 1996
[2] B. J. Baliga, “Fundamentals of Power Semiconductor Devices”, Springer Scientific, New York, 2008.
[3] B.J. Baliga, “Enhancement and Depletion Mode Vertical Channel MOS Gated Thyristors”, Electronics Letters, Vol. 15, pp. 645–647, 1979.
[4] D. Ueda, H. Takagi, and G. Kano, “A new vertical power MOSFET structure with extremely reduced on-resistance,” IEEE Trans. Electron Devices, vol. ED-32, no. 1, pp. 2 – 6, Jan. 1985.
[5] Y. Wang, H.F. Hu, C.H. Yu, H. Lan, “High-Performance Split-Gate Enhanced UMOSFET With p-Pillar Structure”, IEEE Electron Devices, vol. 60, no. 7, pp. 2302 – 2307, 2013.
[6] Y. Wang, H.F. Hu, W.L Jiao, C. Cheng, “Gate Enhanced Power UMOSFET With Ultralow On-Resistance”, IEEE Electron Devices Lett., vol. 31, no. 4, pp. 338 – 340, 2010.
[7] W. Chen, B. Zhang and Z. Li, “SJ-LDMOS with high breakdown voltage and ultra-low on-resistance”, IEEE Electron Lett., vol. 42, no. 22, pp. 1314 -1315, 2006.
[8] X. Yang, Y. C. Liang, G. S. Samudra and Y. Liu, “Tunable oxide-bypassed trench gate MOSFET: Breaking the ideal superjunction MOSFET performance line at equal column width”, IEEE Electron Devices Lett., vol. 24, no. 11, pp. 704 -706, 2003.
[9] S.M. Sze, “Modern Semiconductor Device Physics”, Wiley, New York, Chapter 4, 1997.
[10] Y. Wang, W.L. Jiao, H.F. Hu, Y.T. Liu, J. Gao, “Split-Gate-Enhanced Power UMOSFET With Soft Reverse Recovery”, IEEE Electron Devices, Vol. 60, no 6, pp. 2084-2089, 2013.
[11] Kawashima Y, Inomata H, Murakawa K, Miura Y. Narrow-Pitch N-Channel superjunction UMOSFET for 40–60 V automotive application. In: Proceedings of the 22nd ISPSD and ICs, Hiroshima, Japan, pp. 329–32, 2010.
[12] B.J. Baliga et al., “The Insulated Gate Transistor: A New Three-Terminal MOS- Controlled Bipolar Power Device”, IEEE Transactions on Electron Devices, Vol. ED-31, pp. 821-828,1984
[13] J. D. Plummer, B.W. Scharf, “Insulated-gate planar thyristors: I—Structure and basic operation”, IEEE Trans. Electron Devices, Vol. ED-27, no. 2, pp. 380-387, 1980.
[14] L. Leipold, W. Baumgartner, W. Ladenhauf, and J. P. Stengl, “A FET-Controlled Thyristor in SIPMOS Technology”, IEDM, IEDM Tech. Digest, IEEE, New York, vol. 26, pp. 79-82, 1980.
[15] J. Tihanyi, “Functional Integration of Power MOS and Bipolar Devices”, IEDM, IEDM Tech. Digest, IEEE, New York, vol. 26, pp. 75-78, 1980.
[16] B.J. Baliga et al., “The Insulated Gate Rectifier (IGR): A New Power Switching Device”, IEEE International Electron Devices Meeting, Abstract 10.6, pp. 264–267, 1982.
[17] J.P. Russell et al., “The COMFET”, IEEE Electron Device Letters, Vol. EDL-4, pp. 63–65, 1983.
[18] A Nakagawa, Y. Yamaguchi, K. Watanabe, H. Ohashi, M. Kurata, “Experimental and numerical study of non-latch-up bipolar-mode MOSFET characteristics”, IEEE International Electron Devices Meeting, IEDM Tech. Digest, IEEE, New York, Abstract 6.3, pp. 150–153, 1985.
[19] H. Yilmaz, W.R. Van Dell, K. Owyang, M.F. Chang, “Insulated gate transistor modeling and optimization”, IEEE International Electron Devices Meeting, IEDM Tech. Digest, IEEE, New York, pp. 274–277, 1984.
[20] H.R. Chang and B.J. Baliga, “500-V n-Channel Insulated Gate Bipolar Transistor with a Trench Gate Structure”, IEEE Transactions on Electron Devices, Vol. ED-36, pp. 1824—1829, 1989.
[21] Jun Hu, M. Bobde, H. Yilmaz, A. Bhalla, “Trench shielded planar gate IGBT (TSPG-IGBT) for low loss and robust short-circuit capalibity”, Proc. ISPSD, pp. 25—28, 2013.
[22] J.I. Lee, J. Choi, Y.S. Bae, M.Y Sung, “A novel trench IGBT with a rectangular oxide beneath the trench gate”, ASQED, pp. 370-373, 2009.
[23] H. Nakano et al., “600V trench-gate IGBT with Micro-P structure”, Proc. ISPSD, pp.132—135, 2009.
[24] N. Luther-King, E.M.S. Narayanan, L. Coulbeck, A. Crane, R. Dudley, “Comparison of trench gate IGBT and CIGBT devices for 3.3kV high power module applications”, Proc. SPEEDAM, pp. 545—549, 2010.
[25] W. Fischer, "field Induced Tunnel Diode", IBM Technical Disclosure Bulletin, 1973.
[26] W. Reddiek, G. Amaratunga, "Silicon surface hlnnel transistor" Appl. Phys. Lett., Vol. 61,No. 4,24 July, 1995.
[27] T.Nirschl et al., “The tunneling field effect transistor (TFET) as an add-on for ultra-low-voltage analog and digital processes”, IEEE International Electron Devices Meeting, IEDM Tech. Digest, IEEE, New York, pp. 195—198, 2004.
[28] Alan Seabaugh, “The Tunneling Transistor”, IEEE Spectrum, 2013.
[29] S.M. Sze, “Physics of Semiconductor Devices”, 3rd Ed, Wiley, New York, 2006.
[30] Technology Modeling Associates, Inc., MEDICI (two-dimensional device simulation program), Palo Alto, CA, USA, 2006.

QR CODE