時間至數位轉換器目前廣泛被運用在許多量測儀器與電路中，迄今已發展出各式架構以求在不同需求上獲得解決。其中，游標卡尺法在追求高解析度上為眾多方法中之翹楚，然而其量測範圍無法超過一個參考週期、元件不匹配以致於須使用繁複的校正方式等，在架構上皆是無可避免之缺憾。為此，本研究團隊於2005年率先提出一個具自我校準之游標卡尺法時間至數位轉換器，借重鎖相迴路具自我校準能力，以抑制單級游標卡尺延遲線的電壓、溫度與製程變異，使該架構在不同環境因素下能保有相同解析度，但經實際量測，在量測較長時間寬度時仍有不可小覷的誤差。本論文延續原有架構，針對其架構上的缺陷，將粗計數器之參考脈鐘確實交由鎖相迴路負責，以去除原有複製品不穩定之特性，並改善架構來壓抑上述誤差。於此同時，引入雙倍資料傳輸概念，在電路複雜度近乎不變，和整體頻率完全相同的情況下，使解析度倍增。本電路實現於TSMC 2P4M 0.35μm製程，晶片面積僅有0.342mm2。經由HSpice模擬，預計最佳解析度可達12.5ps，量測頻率在1MHz/sec，解析度在25ps情況下功率消耗60mW。

The time-to-digital converters (TDC) are commonly used in many instrumentation systems or equipments. So far, many kinds of structure were developed for every different requirement. Among these structures, the vernier time-to-digital converter is the best at highly accurate time resolution. However, the input range cannot exceed one period of the reference clock, and the complex calibration mechanism is used for the mismatch between elements. Therefore, a new vernier-based TDC with dual phase-locked loops (PLL) was proposed to improve the two disadvantages, but with wider input range. In fact, when using the TDC in measuring long time period between two signals, there are many errors in this application. In order to improve these problems, we feed the reference clock of coarse counter from the voltage-controlled oscillator in PLL. Besides, with the same circuit complexity and operating frequency, we imply technology of double data rate to increase the time resolution. The proposed TDC has been implemented in 0.35μm standard 2P4M CMOS technology. By simulating in HSpice, the expected time resolution is 12.5ps. The power consumption is 60mW, and the chip size is as small as 0.342mm2.

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