本論文主要目標在於研製500 W半無橋功率因數修正器，其操作頻率設置在300 kHz，並採用寬能矽元件降低其切換損失及採用整合式平面電感降低電路體積，且具有高功率因數、高效率及低電流諧波。文中比較CoolMOS與GaN-FET兩種開關功率元件，以升壓型轉換器作為主架構，採用固定切換頻率及平均電流模式控制，降低輸入電流諧波，並使輸入電流與電壓同相位，達到功率因數修正之目的。論文中分析並驗證整合電感設計，最後實作在線電壓230 Vac時，可達到最高效率η為98%、THD符合IEC61000-3-2之規範以及PF值大於0.96以上。同時也在未來展望提及後續可能的研究方向以提高效率與電路完整性，期待本論文所研製之電路可以更具實用性。

This thesis aims to study and develop a 500-W semi-bridgeless power factor corrector (PFC) with a switching frequency of 300 kHz. Wide band-gap devices and integrated planar inductor are used to reduce switching losses and the converter size. The presented topology features a high power factor, high efficiency and low current harmonics. Two power switches, CoolMOS and GaN-FET, are applied and their performances are compared. The main circuit is a semi-bridgeless boost converter operated with a fixed switching frequency and average current mode control. Therefore, the input current harmonics are reduced and the input current is forced to be in phase with the input voltage to fulfill the power factor correction function. In this thesis, the integrated inductor design is analyzed and validated. The prototype PFC was implemented with a maximum efficiency up to 98% at 230-Vac line voltage. The THD conforms with IEC61000-3-2, and the PF value is higher than 0.96. Future researches are also mentioned to improve the efficiency and integrity of the circuit, hoping that the developed converter in this thesis can be more practical.

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