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研究生: 林彥宇
Yan-Yu Lin
論文名稱: 使用冪圖對多電源領域基板佈局之壓降最佳化
IR-Drop Aware Multiple Power-Domain Substrate Layout Optimization with Power Diagram
指導教授: 劉一宇
Yi-Yu Liu
口試委員: 王國華
Kuo-Hua Wang
陳勇志
Yung-Chih Chen
方劭云
Shao-Yun Fang
學位類別: 碩士
Master
系所名稱: 電資學院 - 資訊工程系
Department of Computer Science and Information Engineering
論文出版年: 2022
畢業學年度: 110
語文別: 英文
論文頁數: 78
中文關鍵詞: 封裝基板電源領域佈局電源傳輸系統冪圖
外文關鍵詞: Package Substrate, Power Plane Layout, Power Delivery System, Power Diagram
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封裝基板是一個載體負責積體電路和印刷電路板之間的電源供給和訊號傳輸。為了維持電源完整性,在封裝基板設計內的電源是使用大面積的舖銅來傳輸的。由於多個電源領域共享同一個基板金屬層,共享的金屬層需要被切割成多個不相交的區域。現今,電源領域佈局通常是由人工去設計的。在此篇論文裡,我們提出一個自動化的結構來完成電源領域佈局。整個結構包含多邊形生成和多邊形優化。在多邊形生成階段,我們提出點分組、邊選擇、邊成本調整的方法來更有效率的產生金屬層中每個領域的多邊形。在多邊形優化階段,我們對於冪圖上的分隔線迭代地採用二分法來同時最佳化多個領域的電阻。實驗結果證明我們的框架可以在考慮壓降的情況下更有效地產生電源平面佈局。得到相容的斯坦納樹所需要的迭帶數是減少了51%。整體的電源領域電阻可以進一步優化11%。


Package substrate is a carrier for power delivery and signal transmissions
between IC and PCB. To maintain power integrity, large copper filled area is used
for power delivery in package substrate design. Since multiple power domains share
the same substrate metal layer, the shared metal layer is required to be partitioned
into several non-overlapped sub-regions. Nowadays, power plane layouts of package
substrates are manually designed. In this thesis, we propose an automated framework to complete the power plane layout. The framework contains two stages, the
polygon generation stage and the polygon refinement stage. In the polygon generation stage, we propose pin grouping, edge selection, and edge cost adjustment
methods to generate polygons efficiently for power domains within the same metal
layer. In the polygon refinement stage, we iteratively adopt bisection method on
division line in power diagram to optimize the resistance of multiple power domains
simultaneously. The experimental results demonstrate that our framework is capable of generating power plane layout efficiently taking IR-drop into considerations.
The number of iterations for obtaining the compatible Steiner trees is reduced by
51%. The overall power domain resistance can be further optimized by 11%.

ABSTRACT List of Tables List of Figures CHAPTER 1. Introduction 1.1 IC Package 1.2 Substrate-Level Power Delivery System CHAPTER 2. Preliminaries 2.1 Problem Definition 2.2 Previous Work CHAPTER 3. Polygon Generation 3.1 Framework 3.2 Pin Grouping 3.3 Edge Cost Adjustment 3.4 Pseudo Node Insertion CHAPTER 4. Polygon Refinement 4.1 Power Diagram 4.2 Bisection Approximation Method CHAPTER 5. Experimental Results CHAPTER 6. Conclusion Bibliography

[1] Yu-Sheng Qin, Xiao-Yu Wang, Yi-Yu Liu, "Power Domain Layer Assignment
in Package Substrate Design," SASIMI, 2021.
[2] Jia-Ming Lee, "Package Substrate Power Plane Layout Partitioning," M. S.
thesis, National Taiwan University of Science and Technology, Taipei, Taiwan,
2021.
[3] IPCB, https://www.ipcb.com/ic-substrate-tech/1120.html.
[4] Mark de Berg, Otfried Cheong, Marc van Kreveld, Mark Overmars, "Computational Geometry: Algorithms and Applications," Springer, 2008.
[5] Power Diagram, https://en.wikipedia.org/wiki/Power diagram.
[6] LayoutEditor, https://layouteditor.com/.
[7] LEDA, http://www.algorithmic-solutions.info/leda manual/Contents.html.
[8] The Computational Geometry Algorithms Library,
https://doc.cgal.org/latest/Manual/packages.html.

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