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研究生: 黃伯庭
Bo-ting Huang
論文名稱: 蔽蔭遮罩圖案畫製作多晶矽薄膜電晶體反相器
Fabrication of Poly-Si TFT CMOS Inverter by Shadow Mask Patterning Process
指導教授: 葉文昌
Wen-chang Yeh
口試委員: 黃鶯聲
none
張勝良
none
學位類別: 碩士
Master
系所名稱: 電資學院 - 電子工程系
Department of Electronic and Computer Engineering
論文出版年: 2009
畢業學年度: 97
語文別: 中文
論文頁數: 60
中文關鍵詞: 多晶矽薄膜電晶體蔽蔭遮罩互補式金氧半場效電晶體
外文關鍵詞: thin film transistor, inverter, shadow mask
相關次數: 點閱:207下載:1
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  • 本研究成功以蔽蔭遮罩圖案化製程製作多晶矽薄膜電晶體和多晶矽反相器,所製作的p型與n型薄膜電晶體其通道長和寬分別為30和80 μm,載子移動率分別為12.19和6.5 cm2/V-s,ION/IOFF電流比分別為6.23×105和4.23×105,臨限電壓分別為-16和6.4V,次臨界擺幅分別為1.2和2.4 V/decade,而多晶矽反相器動態特性為當Vdd和Vss分別為15和0V,其上升時間與下降時間分別為0.79 ms和0.81 ms。


    In this research, we have successfully used shadow mask with all sputter–deposited process to fabricate polysilicon TFTs and polysilicon inverter on SiO2 substrate. The On/Off current ratio, mobility, subthreshold swing, threshold voltage of n-type TFTs are 4.23×105, 6.5cm2/V-sec, 2.4V/dec and 6.4V, respectively. And the parameters of p-type TFTs are 6.23×105, 12.19 cm2/V-sec, 1.2 V/dec and -16.4V, respectively. In polysilicon inverter, it was operated with 200Hz input pulses with a supply voltage Vdd of 15V, the rise time and fall time of output waveform of inverter was estimated to be 0.79 ms and 0.81 ms, respectively.

    第一章 緒論 1-1 前言……………….……………………………… ﹝1﹞ 1-2 金氧半氧化層介紹.……………………………… ﹝4﹞ 1-2.1 载子移動率………………………………………. ﹝5﹞ 1-2.2 臨限電壓…………………………………………. ﹝5﹞ 1-2.3 次臨界擺幅……….……………………………… ﹝6﹞ 1-2.4 開關電比................................. ﹝6﹞ 1-3 研究背景………........................... ﹝7﹞ 1-4 論文流程………….……………………………… ﹝8﹞ 第二章 多晶矽膜之氫稀釋直流濺鍍沉積法 2-1 前言……………….……………………………… ﹝9﹞ 2-2 實驗方法…...…………………………………….. ﹝12﹞ 2-2.1 實驗製程..……………..……………………... ﹝12﹞ 2-2.2 膜質分析…………………………………………. ﹝14﹞ 2-3 實驗結果與討論........................... ﹝15﹞ 2-3.1 氣體流量比值對矽膜結晶性之影響........... ﹝15﹞ 2-3.2 沉積壓力對矽膜結晶性之影響…………………. ﹝16﹞ 2-3.3 矽膜厚度對矽膜結晶性之影響…………………. ﹝18﹞ 2-3-4 载台溫度對矽膜結晶性之影響…………………. ﹝19﹞ 2-4 本章結論………….……………………………… ﹝22﹞ 第三章 蔽蔭遮罩製作多晶矽薄膜電晶體之開發 3-1 前言…………….………………………………… ﹝23﹞ 3-2 實驗方法……….………………………………… ﹝24﹞ 3-2.1 蔽蔭遮罩之設計與薄膜電晶體元件設計………. ﹝24﹞ 3-2.2 濺鍍沉積矽島與源極、汲極摻雜層…………….. ﹝25﹞ 3-2.3 源極、汲極摻雜層之活化技術…………………. ﹝26﹞ 3-2.4 閘極絕緣膜、金屬電極、氫化製程……………. ﹝28﹞ 3-2.5 膜質分析與電性量測……………………………. ﹝30﹞ 3-3 實驗結果與討論……….………………………… ﹝32﹞ 3-3.1 階梯覆蓋性對薄膜厚度之影響…………………. ﹝32﹞ 3-3.2 矽島結晶與S/D摻雜層活化…………………… ﹝36﹞ 3-3.3 多晶矽薄膜電晶體元件特性分析……………… ﹝41﹞ 3-3.4 互補式金氧半場效電晶體元件特性分析……… ﹝51﹞ 3-4 本章結論…….…………………………………… ﹝55﹞ 第四章 總結…………………………………………………. ﹝57﹞ 參考文獻………………………………………………………

    [1] Tadashi Serikawa and Seitti Shirai, “Low-Temperature Fabrication of High- Mobility Poly-Si TFT’s For Large-Area LCD’s”, IEEE vol.36 pp.1929–
    1933(1989)
    [2] Chenhui Wang and Philip J. Bos, “Bistable C1 ferroelectric liquid
    crystal device for e-paper application”, Elsevier Displays vol.25 pp.187–
    194(2004)
    [3] So Yeon Kim, Taek Ahn, Seungmoon Pyo and Mihye Yi, “Surface modified
    polymeric gate insulators for pentacene organic thin-
    film transistors ”,Elsevier Current Applied Physics vol.9 pp.913–918
    (2009)
    [4] 楊朝宇,「介電層表面特性對有機薄膜電晶體的特性影響研究」,碩士論文,國立成
    功大學,台南 (1992)
    [5] R.Mizuki, T. Matsuda, J. S. Nakamura, Y. Takagi, and J. Yoshida, “Large
    domains of continuous grain silicon on glass substrate for high-
    performance TFTs”, IEEE Electron Device Letters, Vol.51 pp.204-211 (2004).
    [6] Y. Takemura and O. Kanagawa, “Method of fabricating a TFT”,United
    States Patent, Vol.437, pp.40-44 (1995).
    [7] K. C. Smith, and A. S. Sedra, “Microelectronic circuits”, Fourth
    Edition, Oxford University Press, Inc. pp.356-367 (1998).
    [8] Minkyu Kim, Jong Han Jeong, Hun Jung Lee, Tae Kyung Ahn, Hyun Soo Shin,Jin-
    Seong Park, Jae Kyeong Jeong, Yeon-Gon Mo, and Hye Dong Kim, “High
    mobility bottom gate InGaZnO thin film transistors with SiOx etch
    stopper”, APPLIED PHYSICS LETTERS,90, 212114(2007)
    [9] Arun Suresh, Patrick Wellenius, Anuj Dhawan, and John Muth, “ Room
    temperature pulsed laser deposited indium gallium zinc oxide channel based
    transparent thin film transistors”, APPLIED PHYSICS LETTERS, 90, 123512
    (2007)
    [10] 陳建利,「InGaZnO4 非晶透明導電薄膜的物性研究與以其製備的薄膜電晶體特性」
    碩士論文,國立交通大學,新竹 (2005)
    [11] Shuichi Uchikoga and Nobuki Ibaraki, “Low temperature poly-Si TFT-LCD by
    excimer laser anneal ”, Elsevier Thin Solid Films
    [12] Yu Chan and Sigurd Wagner, “Inverter made of complementary p and n
    channel transistors using a single directly deposited microcrystalline
    silicon film” , APPLIED PHYSICS LETTERS, vol.75 1125(1999)
    [13] Hiromasa Ohmi, Hiroaki Kakiuchi, Yoshinori Hamaoka, and Kiyoshi Tasutake,
    “Silicon film by chemical transport in atmospheric-pressure pure hydrogen
    plasma ” , JOURNAL OF APPLIED PHYSICS 102,023302(2007)
    [14]陳志強,LTPS低溫複晶矽顯示器技術,全華科技圖書股份有限公司,台北,第5-2頁
    (2004)。
    [15] R. S. Sposili and J. S. Im, “Sequential lateral solidification of thin
    silicon films on SiO2”, APPLIED PHYSICS LETTERS, Vol.69, No.19, pp.2864 - 2866 (1996).
    [16] Gururaj A. Bhat, Zhonghe Jin, Hoi S. Kwok, and Man Wong, “Effects of
    Longitudinal Grain Boundaries on the Performance of MILC-TFT’s” IEEE
    ELECTRON DEVICE LETTERS,Vol.20,NO.2, pp.97-99 (1999)

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