研究生: |
茅哲騏 Che-Chi Mao |
---|---|
論文名稱: |
10 GHz低雜訊快速鎖定頻率合成器晶片設計 10 GHz Low Noise and Fast-Locking Frequency Synthesizer Chip Design |
指導教授: |
黃進芳
Jhin-Fang Huang 劉榮宜 Ron-Yi Liu |
口試委員: |
徐敬文
Ching-Wen Hsue 張勝良 Sheng-Lyang Jang 陳國龍 Ching-Wen Hsue |
學位類別: |
碩士 Master |
系所名稱: |
電資學院 - 電子工程系 Department of Electronic and Computer Engineering |
論文出版年: | 2010 |
畢業學年度: | 98 |
語文別: | 英文 |
論文頁數: | 95 |
中文關鍵詞: | 低相位雜訊 、快速鎖定 、頻率合成器 、鎖相迴路 |
外文關鍵詞: | low phase noise, fast-locking, frequency synthesizer, phase-locked loop |
相關次數: | 點閱:596 下載:3 |
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本論文主要是設計一個10 GHz快速鎖定頻率合成器晶片,此頻率合成器僅使用一個電壓控制振盪器來涵蓋9.2GHz至10.4GHz的頻帶範圍,這個電壓控制振盪器採用互補式交叉耦合架構來獲得低相位雜訊的性能,因此晶片面積能夠被大大的減少。在本論文中使用了一組多係數除頻器電路,藉由改變不同的數位輸入碼能改變通道頻率。藉由妥善的設計系統參數,能使鎖定的時間減少,例如電荷幫浦的電流、電壓控制振盪器的增益與迴路頻寬。
在本論文中,鎖定時間能夠低於3.7us。而此頻率合成器使用台積電所提供0.18微米互補式金氧半製程以1.8伏特來完成所有晶片與量測。量測結果顯示頻率鎖定於10GHz時,距離主頻1KHz至100KHz的相位雜訊低於-60 dBc/Hz,而距離主頻1MHz處的相位雜訊為-113.4 dBc/Hz晶片面積包含pad為0.56 mm2。總消耗功率為39mW。
In the thesis, the proposed 10 GHz fast locking frequency synthesizer chip is presented. The proposed frequency synthesizer can cover the frequency range from 9.2 GHz to 10.4 GHz with only using one VCO and the chip area can be greatly reduced. The VCO employs Complementary cross-coupled structure to obtain lower phase noise performance. In this thesis, the multi-modulus divider (MMD) circuit is also used to change the frequency channel by different input digital code. The locking time can be reduced by carefully design system parameters, such as charge pump current, VCO gain and loop bandwidth.
In this thesis, the locking time is lower than 3.7us. The proposed frequency synthesizer is fabricated in a TSMC 0.18-um CMOS process with 1.8 V supply voltage. The measured results show phase noise is lower than -60 dBc/Hz from 1 kHz to 100 kHz offset and -113.4 dBc/Hz at 1 MHz offset with locked in 10GHz. The chip area of the frequency synthesizer is smaller than 0.56 mm2 including the pads. The power consumption is 39mW from a 1.8V supply.
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