本論文研究主要針對實驗室已開發之奈米碳管整合於矽散熱基板結構做近一步的熱模擬分析及製程步驟之優化改良，並提出利用高熱傳導之陶瓷材料碳化矽(SiC)及離子佈植氬原子的方式，來取代原先基板介電層採用之低熱傳材料一氧化矽(SiO)，近而提升基板整體散熱效率之構想，接著設計不同奈米碳管填充率之散熱基板，並實際量測42mil的紅光LED與不同開口率散熱基板黏合後之L-I-V及熱阻變化趨勢。
模擬成果方面，首先利用CFdesign熱流模擬軟體模擬奈米碳管整合於矽散熱基板的結構，發現基板之介電層若改為理想熱傳導值為400(W/mK)的SiC材料後，其熱阻較原本使用SiO材料之基板降低2成左右。而凹槽開口率越大的基板，因奈米碳管填充率較高的因素，使其熱阻呈現越小的趨勢，當奈米碳管為理想熱傳導值300(W/mK)且凹槽開口率為0.9及凹槽深度為75μm時，熱阻較無凹槽結構之基板降低將近1.5成左右。另外凹槽深度越深的基板，也因奈米碳管填充率較高的因素，使其熱阻呈現越小的趨勢，當凹槽深度達225μm時，整體熱阻較無凹槽結構之散熱基板降低將近3成左右。
實驗成果方面，實際量測LED元件黏合無凹槽結構散熱基板之L-I-V曲線及熱阻後，發現介電層採用陶瓷材料(SiC)之散熱基板有較好的散熱效果，LED之飽合電流較介電層為SiO之散熱基板多提升80mA左右，成功證明本論文提出基板介電層選用高熱傳導係數材料來提升整體散熱效率之構想。而實際量測LED元件黏合不同凹槽結構散熱基板之L-I-V曲線後，發現當基板凹槽結構越大時，LED之L-I曲線呈現的飽和電流值越小。另外利用快速熱阻量測系統量測LED元件黏合不同凹槽結構散熱基板之熱阻後，發現LED黏合不同凹槽結構散熱基板後其熱阻都較沒黏合基板前小，而當散熱基板凹槽越大時，LED的熱阻改善率就越小，當LED黏合無凹槽結構之基板時，LED之熱阻改善率為63%且飽和電流改善量>400mA，而當LED黏合凹槽開口率為0.9之基板時，LED之熱阻改善率下降為11%且飽和電流改善量降低至100mA左右，造成此現象的主要原因為凹槽內側壁無成長奈米碳管所導致的結果，針對凹槽內側壁無成長奈米碳管之散熱基板結構進行模擬後，發現實際量測LED之L-I-V飽和電流及LED熱阻改善變化趨勢與奈米碳管熱傳導值小於300(W/mK)時之模擬熱阻變化趨勢相似，當凹槽越大則封裝後凹槽內的空氣區域就越多，進而抑制散熱基板的散熱效能。

This thesis focuses on detailed thermal and process optimization of the proposed vertically-aligned-carbon-nanotube on silicon (VoS) platform. For practical demonstration, a 42-mil high-power light emitting diode (LED) is used as the heating light source and is bonded onto the VoS platform to investigate the variation of the device performance and the thermal resistance (Rs) of the LED chip. The main contribution of this work is to utilize two different approaches, high-thermal-conductive silicon carbide (SiC) and argon ion implantation, as the current isolation layer (CIL) to replace poor-thermal-conductive silicon monoxide (SiO) that we originally used. Different carbon nanotube (CNT) area ratios are also used in the VoS platform to explore the dependence of CNT area ratios to the overall Rs of the VoS submount. For thermal simulation, a commercialized thermal flow design tool CFdesign is used to investigate the Rs in the VoS platform. The result indicates 20% Rs improvement after replacing originally-used SiO dielectric layer with ideal SiC layer (K=400 W/mK) as the CIL. In addition, the Rs decreases as the CNT area ratio of the VoS submount increases. Another 20% improvement in thermal conduction of the VoS submount could be achieved when the CNT area ratio and U-groove depth are 0.9 and 75 m, respectively. Further increase the U-groove depth to 225 m could even improve the Rs down by 30%. For experimental demonstration, high-power LED chips are bonded on planar submounts with different CILs. The resultant L-I-V curves reveal that the use of SiC as the CIL could lead to the increase of the saturation current by 80 mA as compared to the case for SiO. By replacing planar submounts with the VoS ones which have different CNT area ratios, the saturation current of the bonded LEDs decreases as the CNT area ratio increases. Although the bonded LEDs have smaller Rs compared to the bare chips, the use of VoS submount with larger CNT area ratio does not result in better heat dissipation than planar submount. The use of planar submount would lead to 63% reduction in Rs and the increase of > 400 mA in LED saturation current but the case for VoS platform with a CNT area ratio of 0.9 would only lead to 11% reduction in Rs and the increase of around 100 mA in LED saturation current. We attribute the relatively poor thermal performance in VoS platform to the absence of CNT in the sidewall of the U-groove which would lead to the existence of air gaps beneath the LED chips after bonding, thus increases the Rs. The air gap area increases with the CNT area ratio. Simulation results indicate that as the thermal conductivity of CNT is smaller than 300 W/mK, the thermal benefit from the VoS platform will be cancelled by the air gaps.

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