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研究生: 呂宜靜
Yi-Ching Lu
論文名稱: 三階串接積分器回授型三角積分調變器控制之直流/直流低漣波降壓轉換器
Low Fluctuation DC-DC Buck Converter with 3rd Order CIFB DSM Modulator
指導教授: 姚嘉瑜
Chia-Yu Yao
口試委員: 邱煌仁
Huang-Jen Chiu
陳筱青
Hsiao-Chin Chen
姚嘉瑜
Chia-Yu Yao
學位類別: 碩士
Master
系所名稱: 電資學院 - 電機工程系
Department of Electrical Engineering
論文出版年: 2022
畢業學年度: 110
語文別: 中文
論文頁數: 113
中文關鍵詞: 降壓轉換器三角積分調變器切換式電容積分器超取樣雜訊移頻
外文關鍵詞: Buck Converter, Delta Sigma Modulator, Switched-Capacitor Integrator, Oversampling, Noise Shaping
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  • 傳統的切換式轉換器使用固定開關頻率的PWM(Pulse Width Modulation)做為控制電路,可以達到高效率,但其控制方法容易在輸出上看到固定頻率的漣波電壓。對於較雜訊敏感的RF電路或混訊電路而言,這些漣波與其產生的高次項諧波雜訊容易耦合到基板及供應線上,影響此類電路。因此本篇論文以一離散時間的三階串接積分器回授型三角積分調變器(Discrete Time 3rd Order CIFB Delta Sigma Modulator)當作控制電路的降壓轉換器。
    為了達到低雜訊影響的降壓轉換器,利用三角積分調變器的超取樣及雜訊移頻特性,減少頻寬內的開關雜訊並將其移至高頻。將調變器的輸出結果透過一位元的量化之後,作為控制Power-MOS的開關訊號。量化器調變結果為一頻率不固定且佔空比不固定的訊號,與傳統型的降壓轉換器相比,可降低在輸出看到的雜訊,且頻譜上不會存在明顯的開關頻率。
    本篇論文晶片使用TSMC 0.18um製程,操作電壓為3.3V,降壓轉換器的輸入電壓範圍為3V-3.6V,輸出電壓範圍為1V-3V,取樣頻率為4.95MHz,最大可承受負載電流為800mA,頻譜展示開關頻率在輸入電壓3.3V輸出電壓1.8V時達到-85.32dBm,在輸入電壓3.6V輸出電壓3V且負載電流為200mA時測得最高效率為89.068%,晶片總面積2.76 mm2。


    The traditional switching converter uses a fixed switching frequency PWM (Pulse Width Modulation) as the control circuit, which can achieve high efficiency, but the converters output usually possesses a ripple at the switching frequency. For noise-sensitive RF circuits or mixed circuits, these ripples and their high-order harmonics easily coupled to the substrate and supply lines, affecting the performance of such circuits. Therefore, in this thesis, a discrete time 3rd order cascade integrator feedback(CIFB) delta-sigma modulator (DSM) is used in the buck converter as its control circuit.
    To design a low noise buck converter, oversampling and noise shaping characteristics of a DSM are employed to reduce the in-band switching noise by moving it out of bandwidth. After the 1 bit quantizer, it is used as a switching signal for the power-MOS. The result that the control signal has is a variable frequency and a variable duty cycle. Compared with traditional buck converters, the noise seen at the output can be reduced, and its output spectrum has a relative small tone at the clock frequency.
    The chip is fabricated using the TSMC 0.18um process, .The nominal operating voltage is 3.3V, The input voltage range of the buck converter is 3V-3.6V and the output voltage range is 1V-3V, the DSM clock frequency is 4.95MHz, and the maximum load current is 800mA at 3.3V. The output spectrum shows that the clock tone is suppressed down to -85.32dBm at 3.3V input and 1.8V output. The peak efficiency measured at 3.6V input and 3v output with 200mA load current is 89.068%.The total chip area is 2.76 mm2.

    致謝 i 摘要 ii Abstract iii 目錄 v 圖目錄 viii 表目錄 xiii 第一章 緒論 1 1.1 前言 1 1.2研究動機 1 第二章 三角積分調變器之理論 3 2.1簡介 3 2.2奈奎斯特取樣原理 (Nyquist Sampling Theorem) 3 2.3量化誤差(Quantization Noise) 4 2.4超取樣 (Over-Sampling) 7 2.5雜訊移頻[1] 8 2.6低階三角積分調變器介紹[1] 8 2.6.1一階三角積分調變器 8 2.6.2二階三角積分調變器[1] 10 2.7高階三角積分調變器介紹[1] 12 單迴路架構(Single-loop) 13 第三章 交換式直流/直流降壓轉換器之基本原理 15 3.1簡介 15 3.2開關式直流/直流降壓轉換器分類 16 3.2.1同步整流/非同步整流轉換器 16 3.2.2同步整流型電源轉換器回授控制方式 17 3.3開關式降壓轉換器導通模式[3] 20 3.3.1連續型導通(Continuous-Conduction Mode, CCM)[4][5] 20 3.3.2邊界型導通(Boundary-Conduction Mode, BCM)[4][5] 21 3.3.3不連續型導通(Discontinuous-Conduction Mode, DCM)[4][5] 22 3.4開關式直流/直流轉換器之效能標準[3] 23 3.4.1線性調整率(Line Regulation) 23 3.4.2負載調整率(Load Regulation) 24 3.4.3瞬間暫態響應(Transient Response) 24 3.4.4輸出漣波(Voltage Ripple) 25 3.4.5效率(Power Efficiency) 25 第四章 系統架構分析模擬 27 4.1系統設計簡介 27 4.2 MATLAB Simulink模擬分析 28 4.2.1三階串接積分器迴授型三角積分調變器數學模型 28 4.2.2熱雜訊(Thermal Noise)及閃爍雜訊(Flicker Noise)[7] 32 4.2.3降壓轉換器系統數學模型 34 4.3三角積分調變器架構分析及模擬結果 43 4.3.1Two Stage Single-ended Operational Trans-conductance Amplifier [7] 43 4.3.2 全差動1位元量化器(Fully Differential 1-bit Quantizer) 45 4.3.3非重疊時脈產生器 47 4.3.4 Periodic Steady State(PSS)模擬 49 4.3.5三角積分調變器模擬結果 51 4.4降壓轉換器架構分析及模擬結果 57 4.4.1第三型補償器(Type III Compensator) 57 4.4.2全系統模擬 59 4.5晶片佈局 73 第五章 晶片量測與探討 75 5.1量測環境設定 75 5.2穩壓電路 76 5.3量測結果 76 5.3.1漣波及效率量測 76 5.3.2切換負載量測 82 5.3.3線性調整率量測(Line Regulation) 86 5.3.4負載調整率量測(Load Regulation) 87 5.3.5輸出頻譜量測 88 5.4效能比較表 89 5.5量測檢討 90 第六章 結論與未來展望 93 6.1結論 93 6.2未來展望 93 Reference 96

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