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研究生: 王丹利
Dan-Li Wang
論文名稱: 新型架構QVCO以及八字形電感除頻器之設計
The Design of QVCO with New Structure and Frequency Divider with a 8-Shaped Inductor
指導教授: 張勝良
Sheng-Lyang Jang
口試委員: 黃進芳
Jhin-Fang Huang
王煥宗
Huan-Chun Wang
徐茂修
Mao-Hsiu Hsu
學位類別: 碩士
Master
系所名稱: 電資學院 - 電子工程系
Department of Electronic and Computer Engineering
論文出版年: 2021
畢業學年度: 109
語文別: 英文
論文頁數: 118
中文關鍵詞: 注入鎖定除頻器壓控震盪器鎖相迴路射頻積體電路四相位壓控震盪器八字形電感
外文關鍵詞: ILFD, VCO, PLL, RF, QVCO, 8-shaped inductor
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鎖相迴路(Phase-locked loops)簡稱PLL,是一種利用反饋(Feedback)控制原理來實現頻率以及相位的控制同步技術,鎖相電路目前被廣泛運用在各種領域,如電子計算機、廣播、無線通訊等。在無線通訊系統中,PLL扮演著舉足輕重的腳色,PLL整體大致架構可依序分為鑒相器(PFD)、低通濾波器(LPF)、壓控震盪器(VCO)、除頻器(FD),最後再回到鑒相器(PFD)形成一個完整的迴路。在組成PLL的子電路中,又以壓控震盪器與注入鎖定除頻器特性最為重要,因而本論文主要研究方向為鎖相迴路之壓控震盪器以及除頻器設計。
第四章節中,我們設計了一個有四相位的壓控震盪器(VCO),此VCO採用了TSMC 0.18 μm 1P6M製程,晶片面積為0.859× 0.817 mm2。此電路上分別存在著駐波振盪器(SWO)、行波振盪器(TWO)以及旋轉行波(RTW),其中SWO無法產生多相信號,TWO由於其端接電阻原因而顯示出較差的相位雜訊,而 RTW則可以提供具有良好相位雜訊特性的多相位信號。其中電路中的閉環傳輸線由變壓器以及電容器組成。量測結果為在2.77G以及功耗為11.05mW時,相位雜訊為-123.7dBc/Hz,FOM為-182.6dBc/Hz。
第五章節中, 我們設計了一個寬頻除二注入鎖定除頻器(ILFD)。此除頻器使用TSMC 0.18 μm BiCMOS製程,晶片面積為0.645 ×1.083 mm2。此ILFD使用八字電感做互感耦合,藉以產生兩個諧振頻率,它由兩個子ILFD透過互感耦合組成。透過兩子ILFD的鎖頻範圍不同,以及八字電感可使電路產生兩個頻帶的特性,以達到更寬的鎖定範圍。在高頻頻帶,功耗8.24mW和0dBm的輸入功率下,鎖頻範圍從5.91至10.61GHz。
第六章節中,我們設計了一個寬頻除三注入鎖定除頻器(ILFD),此電路採用的是TSMC 0.18 um CMOS製程,晶片面積為0.859× 0.817 mm2。此ILFD使用了一顆八字電感,並加入P-MOSFET來達成可在current mode與voltage mode之間做切換,藉以探討在此兩種操作模式下之特性。Current mode中,在功耗為8.602mW與0dBm的輸入功率下,鎖定範圍從7.92至11.96GHz,藉由變化P-MOSFET中的VG,可調整電路中電流之大小。Voltage mode中,在功耗為8.376mW與0dBm的輸入功率下,鎖定範圍從7.34至11.73。此ILFD可有兩個以上非完全重疊的鎖定範圍或重疊的鎖定範圍,這表明ILFD不只有單一諧振。


Phase-locked loops, referred to as PLL, is a technology that uses feedback control principles to achieve frequency and phase control synchronization. Phase-locked circuits are currently widely used in various fields, such as electronic computers, broadcasting, and wireless communications. Wait. In wireless communication systems, PLL plays a pivotal role. The overall PLL architecture can be divided into phase detector (PFD), low-pass filter (LPF), voltage controlled oscillator (VCO), frequency divider (FD), and finally back to the phase detector (PFD) to form a complete loop. Among the sub-circuits that make up the PLL, the characteristics of the voltage-controlled oscillator and the injection-locked frequency divider are the most important. Therefore, the main research direction of this thesis is the design of the phase-locked loop voltage-controlled oscillator and frequency divider.

In the fourth chapter, we designed a four-phase voltage-controlled oscillator (VCO), this VCO adopts TSMC 0.18 μm 1P6M process, and the chip area is 0.859×0.817 mm2. There are standing wave oscillator (SWO), traveling wave oscillator (TWO) and rotating traveling wave (RTW) on this circuit respectively. Among them, SWO cannot generate multiphase signals, and TWO shows poor phase due to its termination resistance. Noise, and RTW can provide a multi-phase signal with good phase noise characteristics. The closed-loop transmission line in the circuit is composed of a transformer and a capacitor. The measurement result is that at 2.77G and power consumption of 11.05mW, the phase noise is -123.7dBc/Hz, and the FOM is -182.6dBc/Hz.
In the fifth chapter, we designed a wideband divide-by-two injection-locked divider (ILFD). This frequency divider uses TSMC 0.18 μm BiCMOS process, and the chip area is 0.645 × 1.083 mm2. This ILFD uses eight-shaped inductors for mutual inductance coupling to generate two resonant frequencies. It is composed of two sub-ILFDs through mutual inductance coupling. The frequency lock range of the two sub-ILFDs is different, and the 8-shaped inductance can make the circuit produce the characteristics of two frequency bands to achieve a wider lock range. In the high frequency band, the power consumption is 8.24mW and the input power is 0dBm, the frequency lock range is from 5.91 to 10.61GHz.
In the sixth chapter, we designed a wideband divide-by-three injection-locked divider (ILFD). This circuit uses TSMC 0.18 um CMOS process with a chip area of 0.859×0.817 mm2. This ILFD uses an 8-shaped inductor and adds a P-MOSFET to achieve switching between current mode and voltage mode, so as to explore the characteristics of these two operating modes. In the current mode, under the power consumption of 8.602mW and 0dBm input power, the lock range is from 7.92 to 11.96GHz. By changing the VG in the P-MOSFET, the current in the circuit can be adjusted. In Voltage mode, under the power consumption of 8.376mW and 0dBm input power, the lock range is from 7.34 to 11.73. This ILFD may have more than two non-fully overlapping locking ranges or overlapping locking ranges, which indicates that the ILFD has more than a single resonance.

中文摘要 I Abstract III 致謝 V Table of Contents VII List of Figures X List of Tables XVIII Chapter 1 Introduction 1 1.1 Background 1 1.2 Thesis Organization 3 Chapter 2 Principles and Design Considerations of Voltage Controlled Oscillators 5 2.1 Introduction 5 2.2 Theory of Oscillators 7 2.2.1 Feedback Oscillators 7 2.2.2 Resonator and Negative Resistance 9 2.3 The Classification of Oscillators 12 2.3.1 Ring Oscillator 12 2.3.2 LC-Tank Oscillator 15 2.4 Passive Components Design of VCO 24 2.4.1 Inductor Design 24 2.4.2 Transformer Design 28 2.5 The performance parameters of VCO 36 2.5.1 RF Center Frequency 36 2.5.2 RF Output Signal Power [dBm] 37 2.5.3 Power Consumption [mW] 37 2.5.4 Harmonic/spurious 37 2.5.5 Phase Noise 38 2.5.6 Tuning Range 42 2.5.7 Tuning Sensitivity [Hz/V] 43 2.5.8 Quality Factor 44 Chapter 3 Design of Injection Locked Frequency Divider 47 3.1 General considerations 48 3.2 Operation Range 50 Chapter 4 Quadrature VCO Via Transformer-coupled Transmission Line 53 4.1 Introduction 53 4.2 Circuit Design 54 4.3 Measurement and Simulated 61 Chapter 5 Divide-by-2 Injection-Locked Frequency Divider with 3D Twisted Transformer 66 5.1 Introduction 66 5.2 Circuit Design 66 5.3 Measurement and Simulated 74 Chapter 6 Voltage- and Current-mode ÷3 Injection-Locked Frequency Divider 80 6.1 Introduction 80 6.2 Circuit Design 80 6.3 Measurement and Simulated 85 Chapter 7 Conclusions 94 REFERENCES 96

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