研究生: |
林嘉俊 Chia-Chun - Lin |
---|---|
論文名稱: |
5.5GHz 快速鎖定全數位式鎖相迴路設計 5.5GHz Fast Lock All Digital PLL Design |
指導教授: |
姚嘉瑜
Chia-Yu Yao |
口試委員: |
陳筱青
Hsiao-Chin Chen 彭盛裕 Sheng-Yu Peng |
學位類別: |
碩士 Master |
系所名稱: |
電資學院 - 電機工程系 Department of Electrical Engineering |
論文出版年: | 2017 |
畢業學年度: | 105 |
語文別: | 中文 |
論文頁數: | 89 |
中文關鍵詞: | 相位誤差補償 、頻率誤差補償 、數位控制振盪器 、全數位式鎖相迴路 |
外文關鍵詞: | all-digital phase-locked loop, phase error compensation, frequency error compensation, digitally controlled oscillator |
相關次數: | 點閱:562 下載:0 |
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本論文提出利用新型相位及頻率誤差補償演算法的全數位式鎖相迴路。首先,
我們提出了一個振盪週期對應控制碼呈高解析度的新型數位控制振盪器(DCO)
架構,DCO 採用一般常見LC-tank 架構來控制11-bit dco_code,可提供2048 個
不同的頻率,DCO 振盪頻率約為4.8935GHz-5.9836GHz。
相位誤差補償機制,是利用計數參考訊號Fref 正緣與經除頻器除頻之後產
生的回授訊號Fback 正緣間的數位控制振盪器週期數,藉此修正除頻器除數,以
抵銷Fref 和Fback 間的相差,先解決鎖相迴路追鎖頻率時的相位誤差累積問題,
而其後每個Fref 週期都同時進行頻率誤差與相位誤差補償的機制。
頻率誤差補償的機制是由相位誤差補償機制拓展出來,計數Fback 正緣和
Fref 正緣間的DCO 訊號週期差,以計算控制碼的改變量(ΔCode),達到校正頻率
的功能。
相位頻率誤差補償機制應用在全數位式鎖相迴路的追鎖過程。待系統鎖定後
再藉由拓展控制碼位元數,以增加鎖定後頻率的穩定性。
本論文的晶片是採用TSMC 0.18 um 1P6M CMOS 製程來實現,除了高解析
度的數位控制振盪器、除頻器、DTS 需要採用Full-custom 設計流程完成外,其
餘電路完全可由Cell-Based 設計流程來完成。DCO 操作頻段為5.48 GHz 至
5.62GHz,而其解析度在TT 27℃時介於0.0868ps ~ 0.0891 ps。系統操作功率
消耗為20.538mW 、晶片面積大約為1.965 mm2。
This thesis presents a phase-frequency error compensation mechanism for
an all digital phase-locked lopp(ADPLL). First a novel digital-controlled
oscillator(DCO) was designed. Eleven pairs of symmetrical PMOS varactors are
connected in parallel in the tank circuit. The DCO’s output frequency range is from
4.8935GHz-5.9636GHz.
The phase error compensation mechanism changes the divisor of the divider
to resolve the problem of phase error accumulation by calculating the cycle time
difference between the positive edge of the reference clock and the positive edge of
the feedback signal from the DCO. After that, The frequency error compensation
mechanism is activated to generate the correcting amount of the control-code to fix
the frequency error. Next, the phased-frequency error compensation mechanism is
used in the acquisition mode of the ADPLL. In the tracking mode, after the system is
locked, the control code is extended to enhance the frequency stability.
The proposed ADPLL chip was fabricated in TSMC 0.18um 1P6M CMOS
process. The DCO, Buffer and Divider was implemented by the full-custom design
flow. The other part of the ADPLL is realized by the cell-based design flow. The
DCO’s output frequency range is from 5.48 GHz to 5.62 GHz and its resolution is
between 0.0868 ps and 0.0891 ps at TT 27℃. The power consumption is 20.538
mW, and the chip size is around 1.965 mm2.
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