本論文利用修剪二元樹節點(Binary tree)的方式來簡化原先連續消除解碼(Successive Cancellation，SC)的解碼流程，此種演算法被稱為快速簡化連續消除法(Fast Simplified Successive Cancellation，FSSC)，實作出碼長 (Code length) 為1024、碼率 (Code rate) 為1/2，達到香農極限(Shannon Limit)且具有高工作頻率 (Frequency) 與高吞吐量 (Throughput) 的高效能解碼器。快速簡化連續消除法分類了多種子節點，不同種類的節點有各自的解碼方式，本篇論文提出了八種類型的節點，以此來減少解碼所需的週期數，利用了極化權重（Polarization Weight，PW）來輔助解碼過程中所需要的計算，並使用了半平行化的架構來節省面積。
本論文使用MATLAB 模擬演算法，硬體部分利用硬體描述語言(Verilog) 來進行設計，並使用FPGA開發板進行硬體的驗證，利用TSMC 40nm CMOS 製程技術來進行實作，最後將各項數據與參考文獻進行比較作為本文之結論。

This paper uses the method of pruning binary tree nodes to simplify the original decoding process (Successive Cancellation, SC) which is called Fast Simplified Successive Cancellation (FSSC). By implementing FSSC with code length of 1024 and code rate of 0.5, decoder could reach the Shannon Limit, have high frequency and throughput. FSSC classifies a variety of child nodes, and different types of nodes have their own decoding methods. There are eight types of nodes proposed in this paper, which aims to reduce the number of cycles required for decoding. The Polarization Weight (PW) is used to assist the calculation in the decoding process, while using a semi-parallel architecture to reduce area.
This paper uses MATLAB simulation algorithm, the hardware part uses the hardware description language (Verilog) to design, uses the FPGA development board to verify the hardware, and uses the TSMC 40nm CMOS process technology to carry out the hardware implementation. Item data are compared with references as the conclusion of this paper.

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