本篇論文提出兩個適用於生理訊號感測之類比前端電路中的緩衝放大器。兩者皆使用懸浮閘電晶體編程技術來提供電路的可重構性, 以達到在不同應用情境下皆能符合需求。而在電路架構的發展上，兩者都使用新提出之全電容回授式架構搭配可調動之輸出直流位準及輸入偏移電壓消除能力。其閉迴路增益可透過切換回授電容調整，且不影響電路的輸出直流位準。至於在核心的放大器設計上，研究團隊發展由多種具有ＡＢ類電壓電流特性之電路所組成的超級ＡＢ類架構，使這兩個緩衝放大器整體供應電流可以隨著輸入訊號的特性自動做出調整，且不需要額外的感測或控制電路。當所接收到的輸入訊號頻率較快或是有突然的大振幅變化時，電路的供應電流會自動上升來提供足夠的迴轉率。而當所接收到的輸入訊號頻率較慢或是當電路輸出達到平衡穩態時，電路的供應電流會自動往靜態的低電流方向下降。也正因為所提出的兩種緩衝放大器都有著上述供應電流自動的調整能力，相當合適應用於處理如生理信號般具有突波變化特性的輸入訊號。
所提出的第一個緩衝放大器被設計用以驅動晶片外之量測儀器，並採用差動輸入轉單端輸出的组態以符合大部分量測儀器都為單端輸入的情況。而在放大器設計上，採用二階組態的超級ＡＢ類架構，來確保在不管電容或是電阻式負載時都有足夠的驅動能力。此電路已在0.35 μm 的CMOS 製程下完成晶片下線，其面積為0.109mm2。量測結果顯示該電路具有可調整之閉迴路增益以及輸出入皆有軌對軌的信號擺幅範圍。在1 nF 的電容負載情況下，達到100 kHz 的增益頻寬積的同時，消耗的功耗為25.35 μW，而所量測到的輸入三階截斷點為39.21 dBV，迴轉率為0.5 V/ μs。
而本篇論文所提出的第二個緩衝放大器，則是被設計來做為循序漸進式類比數位轉換器的輸入驅動電路。由於僅有電容式負載需要驅動，在內部放大器的架構則選用具ＡＢ類電流電壓特性的單級伸縮疊接阻態來達成更低的功率消耗。其概念驗證的晶片已在0.35 μm 的CMOS 製程下完成電路模擬和下線。此晶片具有閉迴路增益從6 dB 到36 dB 的切換範圍，而在1.2 pF 的電容負載下，模擬結果顯示達到1.28 MHz 的單增益頻寬下，所需消耗的功率消耗僅12.5 μW。此外電路的線性度模擬結果顯示在輸出擺幅為2.4Vpp 其總諧波失真為87 dB, 另外在two tone test 情況下所計算出之輸入三階截斷點為26.51 dBV。而在步階響應的模擬中所得到的平均迴轉率為5.043 V/ μs。

Two powerefficient
buffer amplifiers utilized in biomedical sensing analog front-end (AFE) chain are proposed in this thesis. Floating gate transistors technique is employed
in both of them to provide circuit reconfigurability to meet requirements under different application. Fully capacitive feedback topology with adjustable output DC level and input offset trimming function are adopted as their main structure. Closed-loop gain for both of them is adjustable and output DC level is independent with gain setting. As for the core amplifier design, super class-AB
architecture with multiple class-AB techniques has been developed to provide the ability of autonomous supply current adaptation according to the characteristic of input signal. Without extra sensing and control circuit, the current consumption of these buffer amplifiers increase spontaneously to provide sufficient slew rate when the input frequency is high or when input signal has a large abrupt change. The supply current dwindles back to low quiescent levels autonomously when the input is slow or when the output voltage reaches equilibrium. Since current consumption is adaptive to both frequency and amplitude of input signal, they are suitable to process physiological
signals with spike-like characteristic.

The proposed first buffer amplifier is design for driving subsequent measurement instrument. This buffer develops a differential to single-ended
configuration ,and the core amplifier adopts two-stage super class-AB architecture to provide sufficient driving capabilities for both resistive and capacitive loads . Those characteristics are indispensable to transmit signals to off-chip. A concept proving chip has been designed and manufactured
in a 0.35 μm CMOS process occupying an area of 0.109 mm2 with variable gain and rail-to-rail input and output swing ranges. When measured under 1 nF capacitor loading, it consumes 25.35 μW to achieve gainbandwidth
product of 100 kHz with measured IIP3 of 39.21 dBV and a slew rate of 0.5 V/ μs.

The second buffer amplifier with fully differential configuration are proposed as input driver circuit of subsequent ADC. Since only capacitive loading need to drive, the core amplifier adopts a class-AB single stage telescope topology for more power saving. A concept proving chip has been designed and fabricated in a 0.35 μm CMOS process with variable gain option from 6 dB to 36 dB. The proposed buffer amplifier is simulated under lowest gain and 1.2 pF ADC Capacitor array as loading. The unit gain bandwidth is programmed to 1.28 MHz with static power consumption is 12.5 μW. The linearity performance shows that total harmonic distortion is 87 dB with 2.4Vpp output swing, and extracted IIP3 is 26.51 dBV under two tone test. The simulating step response shows that average slew rate is 5.043 V/ μs.

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