本篇論文提出適用於生醫應用之高功率效能雙通道類比前端感測電路設計並
且使用懸浮閘編程技術，在類比前端的每個通道之電路包含了一個低雜訊放大
器、一個可變增益放大器、兩個可重組化雙二階濾波器和一個緩衝放大器。懸浮
閘電晶體被用來實現可編程電流源、共模回授電路與可編程線性偽電阻，並達到
低雜訊、高線性度與低功率消耗。由於電流源是可編程的，電路頻寬很容易地根
據不同的物理訊號感測之應用做調整，像是偵測人體之心電圖、腦波圖和肌電
圖。所提出的類比前端電路以0.35微米互補式金氧半製程所製造，它的面積為
6.88毫米平方公分。為了防止濾波器影響低頻訊號的靈敏度，所設計的感測通道
包含了低雜訊放大器和可變增益放大器，在205奈安培的電流消耗之下，達到了
116赫茲的高頻截止點與0.8赫茲的低頻截止點。中頻增益的設計範圍從55.35分
貝至81.58分貝。在積分從0.5赫茲到100千赫茲之下，所測量的輸入參考雜訊電
壓為2.43微均方根伏特。雜訊效率因素為3.94。在低增益設定之下，總斜坡失真
為-58.34分貝且輸出峰對峰值為1.136伏特。
由於可變增益放大器採用T 型網路去實現小回授電容值，為了達到一個低頻
截止點，回授偽電阻值會大於位於低雜訊放大器的阻值數倍。為了改善這項缺點，
這個可變增益放大器被重新設計，且透過採用原始結構的緩衝放大器。由於使用
懸浮閘之具有增強迴轉率的AB類輸入級，相比於傳統運算放大器之下線性度被
改善。頻寬和閉迴路增益都可調整，需透過懸浮閘電流源與切換不同回授電容的
數量。被改善後的緩衝放大器被設計與製造在0.35微米互補式金氧半製程，佔據
的矽面積為0.084毫米平方公分。在100千赫茲、500千赫茲與1兆赫茲情況之
下，電流消耗分為5.9微安培、38微安培與124.8微安培。所測量到的三階輸入
截止點在28.7分貝伏特以上，總諧波失真在低增益設定時為-82.6分貝之下。

This thesis presents the design of power-efficient dual channel analog front-end (AFE) circuits for biomedical applications based on floating-gate programming technologies. The circuits in each channel of the analog front-end include a low noise amplifier (LNA), a variable gain amplifier (VGA), two reconfigurable biquadratic filter sections, and a buffer amplifier (BA). Floating-gate transistors are employed to implement programmable current sources, common-mode feedback, and programmable linear pseudo resistors, achieving low noise and high linearity with low power consumption. Since the bias current level is programmable, the bandwidth of the circuits can be easily tuned to fit into a variety of physiological signal sensing applications, such as the electrocardiogram (ECG), electroencephalogram
(EEG), and electromyogram (EMG) from human bodies. The proposed AFE was fabricated in a 0.35μm CMOS process, and its area is 6.88mm2. To prevent that the filter impacts the sensitivity of the low frequency signal, the designed sensing
channel includes the LNA and the VGA, achieving 116Hz of the high frequency cutoff
point and 0.8Hz of the low frequency cutoff point under 205nA of current consumption. The midband gain is designed from 55.35dB to 81.58dB. The measured input referred noise voltage is 2.43Vrms integrated from 0.5Hz to 100kHz. The noise efficiency factor (NEF) is 3.94. The total harmonic distortion (THD) is -58.34dB with 1.136V of the output peak-to-peak voltage in the low gain set.

Since the variable gain amplifier employs T-network to implement the small feedback
capacitance, the feedback pseudo resistance should be several times larger than that in LNA to achieve a low frequency cutoff point. To improve this drawback, the variable gain amplifier is redesigned by employing the original structure of the buffer amplifier. Compared with conventional operational amplifier, the linearity is improved because of the floating-gate based class-AB input stage with enhanced slew rate. The bandwidth and the closed-loop gain are both reconfigurable through programming the floating-gate current source and switching different amount of feedback capacitors. The improved buffer amplifier was designed and fabricated in a 0.35μm CMOS process occupying a silicon area of 0.084mm2. The current consumptions under 100kHz, 500kHz, and 1MHz conditions are 5.9μA, 38μA, and 124.8μA, respectively. The measured IIP3 is above 28.7dBV, and the THD is below -82.6dB in the low gain set.

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