本論文分為兩個主題，第一個研究主題將類比數位轉換器與輸入驅動器兩大電路整合，並應用於類比前端感測電路中，採用逐漸逼近式之類比數位轉換器架構與自適電流調變輸入驅動器，進而達到降低電路功耗之目標；第二個研究主題則提出位準交越式及逐漸逼近式混合架構之不規律採樣類比數位轉換器，並應用於生理訊號感測，透過逐漸逼近式架構於類比數位轉換之低功耗優點，結合位準交越式架構於穩態時之超低功耗，進而達到降低電路功耗之目標，此外，由於採用不規律取樣與位準交越式架構，更可以較低位元數達成較高之線性度。
　　第一部分電路實現於台積電0.35μm 2P4M 互補式金屬氧化物半導體技術，為達成低功耗之目標，電路中輸入驅動器採幫浦電路AB 類放大器架構，藉以達成電流自適應調變，訊號於追蹤階段產生較大供應電流，使驅動器擁有足夠迴轉率，反之，隨著輸入驅動器進入穩定階段，電路亦將自主降低供應電流至靜態電流。此外，本電路除了於迴受架構上採全電容式，透過切換不同電容陣列亦可改變增益；並在偏壓電流、共模迴受、輸入電壓以及疊接電壓等處加入懸浮閘電晶體，透過編程技術替整體電路增加更高之電路可重構性。後端整合之類比數位轉換器採逐漸逼近式架構，取樣頻率為200 kHz ，受惠於逐漸逼近式類比數位轉換器之低功耗電路特性，且此架構之適用解析度與類比前端感測電路應用之生理訊號十分契合，考量到晶片封裝與印刷電路板寄生所致之電壓震盪，電路中亦加入參考電壓緩衝電路以降低其影響。輸入訊號頻率為奈奎斯95.31 kHz 且輸入振幅為2.8 V pp 時，驅動器總諧波失真為−70.1 dB ，於奈奎斯頻率下且追蹤相位10% 時，與傳統電路架構相比，可節省49.5% 的功耗。所量測之無雜散動態範圍與信號雜訊失真比率分別為60.53 dB 和56.51 dB ，有效位元數為9.1 位元。
　　另一部分研究則為不規律採樣之位準交越式類比數位轉換器的電路創新，應用領域為生理訊號，實現於台積電0.18μm 1P6M 互補式金屬氧化物半導體技術，電路中將量化器由逐漸逼近式類比數位轉換器取代傳統的單一比較器基底或是快閃式類比數位轉換器；此外，於位準交越之偵測上，透過具幫浦電路之靜態比較器與動態鄰近比較器相互進行位準偵測。當輸入訊號頻率為10 kHz ，採樣解析度為4000 時，所量測之無雜散動態範圍為56.195 dB ，有效位元數為9.04 位元。總消耗功率為9.16μW，等效電源轉換率為870fJ/Conversion − step。

This thesis is separated into two sections. In the first part of the research, an analog-to-digital converter(ADC) and input driver are integrated into one chip for the analog-front-end(AFE) sensing circuit. Successive-approximation-register(SAR) topology is adopted in the data converter. As for the input driver, autonomous current adaption is implemented. With these two topologies, lower power consumption can be achieved. The second section of the thesis proposed a non-uniform sampling level-crossing(LC) hybrid SAR ADC, which is suitable for biomedical signal sensing—combined the low power consumption advantage of the SAR ADC structure and the LC ADC’s ultra-low power consumption during the steady state. Therefore, the total power consumption can be low. Moreover, due to the non-uniform sampling and the LC topology, higher linearity can be achieved by the lower resolution ADC.
　　In the first section, the prototype version of the proposed circuit has been designed and fabricated in a 0.35μmtwo-poly-four-metal(2P4M) complementary metal oxide semiconductor(CMOS) process. In order to fulfill the low power consumption goal, the input driver adopts the class AB topology to achieve autonomous current adaption. During the tracking phase, the input driver will generate a higher bias current to provide enough slew rate. On the other hand, the bias current will gradually recover to a quiescent current in the steady state. Besides, the proposed circuit adopts the fully capacitive feedback structure, and the variable gain can be utilized by switching different capacitor arrays. Furthermore, the reconfigurability is provided by program the floating gate transistors, which are employed at bias current, common-mode feedback, input common-mode voltage, and cascode biasing. The integrated ADC adopts SAR topology, while the sampling rate is 200 kHz. Benefiting from the low power circuit characteristics of the SAR ADC and the compatible resolution and physiological signal applications of the AFE sensing circuit in this architecture. Considering the voltage undershoot caused by the parasitic inductance of the chip packaging and the PCB board, a reference voltage buffer circuit has been designed in the chip to reduce its errors. As a result, when the input frequency in Nyquist frequency of 95.31 kHz, and the input amplitude of 2.8 V pp. The total harmonic distortion(THD) reaches −70.1 dB. Compared to the conventional structure, the proposed input driver can reduce 49.5% of power consumption in Nyquist frequency under the tracking period of 10%. The measured spurious-free dynamic range (SFDR) and the signal noise distortion ratio(SNDR) are 60.53 dB and 56.51 dB. Therefore, the effective number of
bits(ENoB) is 9.1bit.
　　The other part of the thesis introduces the non-uniform sampling LC ADC innovation for biomedical signal sensing. The prototype version of the proposed circuit has been designed and fabricated in a 0.18μmone-poly-six-metal(1P6M) CMOS process. The conventional quantizer, single comparator-based or flash-based ADC, is replaced by SAR ADC. The static comparator with bump cell and the dynamic proximity comparator are adapted to detect the level-crossing. When the input frequency is 10 kHz and the time resolution is 4000, the measured SFDR is 56.195 dB, so that the ENoB is 9.04bit. The total power consumption is 9.16μW. As a result, the equivalent power conversion rate is 870fJ/Conversion − step.

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