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研究生： 葉婷
Ting - Ye
論文名稱： 應用於無線感測器之逐次逼近式低電壓類比數位轉換器晶片設計
The 10-bit 2-MS/s Low Voltage SAR ADC Chip Design for Wireless Sensor Applications
指導教授： 劉榮宜
Ron-Yi Liu
黃進芳
Jhin-Fang Huang
口試委員: 徐敬文
Ching-Wen Hsue
江正雄
Jen-Shiun Chiang
張勝良
Sheng-Lyang Jang
學位類別： 碩士
Master
系所名稱： 電資學院 - 電子工程系
Department of Electronic and Computer Engineering
論文出版年： 2012
畢業學年度： 100
語文別： 英文
論文頁數： 87
中文關鍵詞： 低電壓 、逐次逼近式類比數位轉換器 、時間交錯式
外文關鍵詞： time-interleaved, SAR ADC, low voltage
相關次數： 點閱：310  下載：12 
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    • 本論文中討論以TSMC 1P6M 0.18 μm CMOS製程，實現一個十位元、每秒兩百萬次取樣時間之逐漸逼近式類比數位轉換器，以及90 nm 八位元、每秒八千萬次取樣頻率之時間交錯技術逐漸逼近式類比數位轉換器。十位元類比數位轉換器中的數位類比轉換器為了有較高的準確度，使用二進位加權電容陣列。取樣保持電路包含靴帶式電路以提升電路效能。兩級的動態比較器有較佳的電壓偏移，以及不需額外偏壓電路，可節省功率消耗。此外，十位元類比數位轉換器時脈訊號為取樣頻率的20倍，八位元類比數位轉換器時脈訊號即為取樣頻率。
    經由HSPICE和SpectreRF輔助設計軟體驗證結果，0.18 μm十位元以及90 nm 八位元逐漸逼近式類比數位轉換器被實現，其中下線的十位元晶片有量測結果。在供應電壓為1 伏特下，量測差分非線性度及積分非線性度為 0.97 LSB和2.23 LSB。當輸入訊號為200 kHz下，其量測所得有效位元為8.12-bit，本晶片面積包含ESD PADs為0.7 mm2，整體電路功率消耗為126 μW。

    In this thesis, a 10-bit 2-MS/s Successive Approximation Register analog-to-digital converter (SAR ADC) implemented in TSMC double-poly six metal (1P6M) 0.18-μm CMOS technology and a 90 nm 8-bit 80-MS/s time-interleaved (TI) SAR ADC are introduced. The digital-to-analog converter (DAC) of the 10-bit SAR ADC is accomplished by charge redistribution binary weighted capacitor array based on its accuracy. The track-and-hold (T/H) circuit includes bootstrapped circuit improving T/H performance. The comparator structure is a two-stage dynamic comparator which helps reduce offset voltage and has no external biasing voltage so that low power consumption is achieved. For the 10-bit ADC, an external frequency which is 20 times the frequency of the 2 MHz sampling rate is needed. For the 8-bit TI SAR ADC, the clock frequency is the sampling rate.
    The SAR ADCs are simulated by HSPICE and SpectreRF. The 10-bit ADC is taped out by TSMC excluding the 8-bit 90 nm ADC. The measurement results of differential and integral nonlinearity of the 10-bit ADC are within 0.97/-0.86 LSB (Least Significant Bit) and 1.63/-2.23 LSB respectively at full sampling rate. The measurement results show effective number of bit (ENOB) of 8.12-bit with sampling frequency of 2 MHz at input frequency close to 200k Hz. The chip area including ESD (electrostatic discharge) pads is 0.7 mm2. Power consumption of this ADC is 126 μW with 1 V supply voltage.

    CHAPTER 1 Introduction 1 1.1 Motivation 1 1.2 Focus and Contributions 2 1.3 Organization of This Thesis 3 CHAPTER 2 Fundamentals of Analog-to-Digital Converter 4 2.1 Introduction 4 2.2 Basic Concepts 4 2.2.1 Differential Nonlinearity (DNL) 4 2.2.2 Offset Error 5 2.2.3 Gain Error 6 2.2.4 Missing Codes 6 2.2.5 Integral Nonlinearity (INL) 7 2.2.6 Signal-to-Noise Ratio (SNR) 7 2.2.7 Signal-to-Noise and Distortions Ratio (SNDR) 8 2.2.8 Spurious Free Dynamic Range(SFDR) 8 2.2.9 Resolution and Effective Number of Bits (ENOB) 8 2.2.10 Coherent Sampling 9 2.3 Architectures of Analog-to-Digital Converters 9 2.3.1 Flash ADC 9 2.3.2 Two-Step Flash ADC 10 2.3.3 Time-Interleaved ADC 11 2.3.4 Pipelined ADC 12 2.3.5 Successive Approximation ADC 13 2.3.6 Sigma-Delta ADC 14 2.3.6 Conclusion 15 2.4 Papers’ Survey 16 2.5 Summary 20 CHAPTER 3 Chip Design of the 10-bit SAR ADC 22 3.1 Introduction 22 3.2 Design Specifications 24 3.3 Circuits Level Design 24 3.3.1 Track-and-Hold Circuit 24 3.3.2 Comparator 28 3.3.2.a Architecture 31 3.3.2.b Specifications 31 3.3.2.c Simulation Results 32 3.3.3 Digital-to-Analog Converter 38 3.3.3.a Charge Redistribution DAC 38 3.3.3.b Clock Feedthrough 40 3.3.3.c Unit Capacitor Sizing, kT/C Noise and Quantization Noise 43 3.3.3.d Switch sizing 44 3.3.3.e Placement of Capacitors and Mismatch of Capacitor Array 45 3.3.4 SAR Control Logic Circuit 47 3.3.5 Clock Generator Circuit 49 3.3.6 Digital Buffer Circuit 50 3.4 SAR ADC Simulation Results 53 3.5 Chip Measurement Considerations for SAR ADC 58 3.5.1 Chip Floor Plan and PCB Design 59 3.5.2 Measurement Instrument 61 3.5.3 Measurement Results 62 3.6 Summary 64 CHAPTER 4 Time-Interleaved 8-bit 80-MS/s SAR ADC 66 4.1 Introduction 66 4.2 Time-Interleaved SAR ADC Architecture 67 4.3 Simulation Results of Time-Interleaved SAR ADC 77 4.4 Summary 78 CHAPTER 5 Conclusions and Future Work 80 5.1 Conclusions 80 5.2 Future Work 81 References 84 Appendix 85

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