研究生: |
呂騰傑 Teng-chieh Lu |
---|---|
論文名稱: |
升壓型功率因數修正器之類比乘法器研製 Design of an Analog Multiplier for Boost Power Factor Corrector |
指導教授: |
羅有綱
Yu-kang Lo 邱煌仁 Huang-jen Chiu 劉邦榮 Pang-jung Liu |
口試委員: |
歐勝源
Sheng-yuan Ou |
學位類別: |
碩士 Master |
系所名稱: |
電資學院 - 電子工程系 Department of Electronic and Computer Engineering |
論文出版年: | 2012 |
畢業學年度: | 100 |
語文別: | 中文 |
論文頁數: | 68 |
中文關鍵詞: | 功率因數修正器 、類比乘法器 、超高壓製程 |
外文關鍵詞: | power factor corrector, analog multiplier, ultra-high voltage |
相關次數: | 點閱:260 下載:11 |
分享至: |
查詢本校圖書館目錄 查詢臺灣博碩士論文知識加值系統 勘誤回報 |
近年來功率因數修正器在交換式電源供應器中扮演相當重要的角色。本論文提出一個可用於功率因數修正器的類比乘法器。此乘法器將輸入電壓與回授電壓相乘得到的訊號,來控制輸入電流。本論文將可變線性電阻應用於非反相放大器,藉由改變輸入電壓可以控制可變電阻大小,來改變非反相放大器的電壓增益,如此即可實現乘法器。相較於其他文獻,本論文所提出的乘法器具有較大的輸入範圍,且為單端輸入單端輸出。
本晶片使用TSMC 0.5-μm 800 V超高壓製程來實現,晶片大小為3.56×2.56 mm2。輸入電壓範圍為交流90至264 V,輸出電壓為400 V。外接電感感值為2 mH,外接電容容值為10 μF,本晶片最小的操作頻率為30 kHz。模擬結果顯示,當誤差放大器輸出電壓從2.5 V~5 V時,乘法器的總諧波失真皆小於4%。
In recent year, power factor correctors play an important role in switching power supplies. This thesis proposes an analog multiplier that can be applied to power factor correctors. The input current is controlled with the multiplier output, which is obtained by multiplying the input voltage and voltage feedback. The proposed analog multiplier is realized with a variable linear resistor applied to a non-inverting amplifier, whose voltage gain is tuned with the input voltage to control the value of the variable linear resistor. Compared with previous works, the proposed multiplier has the advantages of a large input range and single-ended input to single-ended output.
This chip had been fabricated with TSMC 0.5-μm 800 V ultra-high voltage process, and its size is 3.56×2.56 mm2. The input voltage is from AC 90 V to 264 V and the output voltage is 400 V. The off-chip inductance is 2 mH, the output capacitance is 10 μF, and the minimum operation frequency is 30 kHz. Simulation results show that the total harmonic distortion of the multiplier is less than 4% when output voltage of the error amplifier is from 2.5 to 5 V.
[1]黃建淳,250 W局部零電壓切換諧振升壓型功率因數修正器之研製,國立台灣科技大學電子工程系碩士論文,民國98年。
[2]N. Mohan, T. M. Undeland and W. P. Robbins, “Power Electronics: Converters, Applications and Design,” New York: Wiley&son Inc., 3rd Edition, 2003.
[3]陳冠廷,具功率因數修正器開關功能之雙模返馳式轉換器研製,國立台灣科技大學電子工程系碩士論文,民國99年。
[4]A. I. Pressman, “Switch Power Supply Design,” Second Edition, McGraw-Hill, 1998.
[5]梁適安,交換式電源供應器之理論與實務設計,民國83年,全華科技圖書。
[6]陳文富,200瓦LED路燈電源供應器研製,國立台灣科技大學電子工程系碩士論文,民國99年。
[7]G. Han and E. Sanchez-Sinencio, “CMOS Transconductance Multiplier: a Tutorial,” IEEE Trans. Circuit Syst., Analog Digit. Singal Process., vol 45, no.12, pp. 1500-1563, Dec. 1998.
[8]A. L. Coban and P. E. Allen, “Low-voltage CMOS Transconductance Cell Based on Parallel Operation of Triode and Saturation Transconductors ,” Electron. Lett., vol 30, pp.1124-1126, July 1994.
[9]H. Song and C. Kim, “An MOS Four-Quadrant Analog Multiplier Using Simple Two-Input Squaring Circuit with Source Follower,” IEEE J. Solid-State Circuits, vol 25, pp.841-848, June 1990.
[10]B. Gelbert, “A Precision Four-Quadrant Multiplier with Subnanosecond Response,” IEEE J. Solid-State Circuits, vol 3, pp.353-365, Dec 1968.
[11]B. Razavi, “Design of Analog CMOS Integrated Circuits,” New York: McGraw-Hill, 2001.
[12] G. A. Hadgis and P. R. Mukund, “A Novel CMOS Monolithic Analog Multiplier with Wide Input Dynamic Range,” in Proc. Int. Conf. VLSI Design, New Delhi, India, pp.310-314, 1995.
[13] G. Moon, M. E. Zaghloul and R. W. Newcomb, “An Enhancement-mode MOS Voltage-controlled Linear Resistor with Large Dynamic Range,” IEEE Trans. Circuit Syst., vol 37, no.10, pp.1284-1288, Oct.1990.
[14]C. F. Lee, P. K. T. Mok, “A Monolithic Current-Mode CMOS DC-DC Converter with On-Chip Current-Sensing Technique,” IEEE J. Solid-State Cicuits, vol 55, no. 8, pp. 1150-1154, Aug. 2008.
[15]“L6561, Enhanced Transition-Mode Power Factor Corrector,” AN966, www.st.com.
[16]R. J. Baker, H. W. Li and D. E. Boyce, “CMOS Circuit Design, Layout, Simulation,” IEEE Press, John Wiley and Sons, Inc., 1998.