矽光電將成為下世代的光電、通訊及電子產業帶來革新。這個新技術因能提供與現有的互補金屬氧化半導體製程相容的優勢，許多的團隊對此研究感到關切。近幾年來的進展將使得商用化的矽光電應用產品於不久的將來出現。基於研究的角度，建立矽光電的基礎架構是一個必要的開始。因此，藉由以絕緣層上覆矽晶圓為平台的的波導設計及應用標準的互補金屬氧化半導體製程將在本文中詳細探討。

我們設計工作波段於1550奈米的單模脊狀光波導，此微米級的絕緣層上覆矽晶圓之波導結構高為5微米，寬為5微米，板高為2.5微米藉由互補金屬氧化半導體中的乾式蝕刻以六氟化硫、三氟甲烷和氧的電漿所製作而成的。此脊狀波導擁有近90度的側壁結構、約12奈米粗糙度的蝕刻表面及蝕刻非均勻度僅0.07微米的標準差，而側壁的粗糙度藉掃描電子顯微鏡的觀察約僅數十奈米。在此波段上實現此波導的傳輸損耗約為1.1dB/cm。陣列波導光柵也藉此製程量測得約有23.9 dB的串音。

Silicon photonics is considered to be the next leap in optoelectronics, telecommunication, and electronics industries. This technology has gained its tremendous attention and research interests due to its capability in compatible with existing CMOS fabrication process. The advances in the recent years have made it possible to commercialize many newly developed components and systems in the very near future. In engaging in this research, the establishment of fundamental building blocks is mandatory. The silicon-on-insulator (SOI) waveguides were designed and fabricated within a standard CMOS research context.

The single mode optical ridge waveguide was designed at the wavelength of 1550 nm. This micrometer size SOI ridge waveguides with height of 5.0 μm, width of 4.5 μm, and slab height of 2.5 μm were realized with dry etching on CMOS compatible SF6/CHF3/O2 reactive ion etching system. The ridge waveguide providing the profile angle at nearly 90°, etched surface roughness of 12 nm, and etched wafer non-uniformity of μm was fabricated. Sidewall roughness of several tens of nanometer is determined with scanning electron microscope inspection. The propagation loss of 1.1 dB/cm was determined for the fundamental mode at the wavelength of 1550 nm. The arrayed waveguide grating was implemented with this process to yield a crosstalk of 23.9 dB.

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