應用於MIMO無線通訊系統之低延遲高速度排序QR分解電路架構設計與實現

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研究生：	陳威揚 Wei-Yang Chen
論文名稱：	應用於MIMO無線通訊系統之低延遲高速度排序QR分解電路架構設計與實現 The VLSI Architecture of a Low-Latency High-Throughput Sorted QR Processor for MIMO Systems
指導教授：	沈中安 Chung-An Shen
口試委員:	林昌鴻 Chang-Hong Lin 王煥宗 Huan-Chun Wang
學位類別：	碩士 Master
系所名稱：	電資學院 - 電子工程系 Department of Electronic and Computer Engineering
論文出版年：	2015
畢業學年度：	103
語文別：	英文
論文頁數：	39
中文關鍵詞：	多輸入多輸出、排序QR 、低延遲、座標旋轉運算器
外文關鍵詞：	MIMO, Sorted QR, Low latency, CORDIC
相關次數：	點閱：379 下載：15
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隨著通訊技術的成熟，人們對於無線傳輸速度的要求越來越高，而多輸入多輸出(Multiple-Input Multiple-Output, MIMO)無線通訊技術已被廣泛認可為提高資料傳輸速率的最有效方法之一。MIMO系統之核心概念為使用多根發送天線與多根接收天線技術提供空間自由度以有效提升無線系統之頻譜效率，並藉由多條路徑傳播的特點提高傳輸通訊量、傳輸距離/覆蓋範圍以及可靠性。然而，在另一方面，MIMO技術卻也導致運算的複雜度增加，使得系統運算延遲上升並因此影響處理速度。因此，如何在MIMO系統中設計低延遲及高處理速度之電路元件便至關重要。
訊號偵測(Signal Detection)是MIMO系統中最重要且運算量最龐大的元件之一。通常一個MIMO訊號偵測元件需要對資料進行前置處理，而其中以排序型QR(Sorted QR)分解技術最被廣泛採用。由於排序型QR分解電路牽涉到大量矩陣運算因此嚴重影響MIMO系統的延遲時間與處理速度。本論文描述應用於MIMO無線通訊系統之低延遲高速度排序QR 分解電路架構設計與實現，在此設計中，我們使用提出了混和式座標旋轉運算法(Hybrid-CORDIC)計算範數，並且與吉文斯旋轉(Givens Rotation)結合的策略，實現排序QR分解的處理器，而其架構採用全流水線(Fully-Pipeline)的設計藉此達到高吞吐量(High Throughput)。
在接下來的文章中，我們將詳細的介紹我們的排序QR分解的硬體架構。本設計是在台積電90奈米製程的環境下實現，電路佈局後(post layout)的實驗結果顯示，本研究最高可達232.56MHz，並且吞吐量每秒可處理58.1百萬個排序型QR分解的運算。

This thesis presents the VLSI architecture of a low latency, high throughput Sorted-QR (SQR) decomposition processor for MIMO communication systems. The proposed SQR engine is operating directly on the complex-valued channel matrix to avoid the matrix augmentation caused by the real-valued decomposition of the channel matrix. Furthermore, in order to improve the timing efficiency, a pipelined Givens Rotation engine is employed and a novel structure based on the multi-dimensional CORDIC circuit is utilized to perform the rotation. In addition, in this design, the computation of norm can be generated as a by-product of the vectoring in the CORDIC operation such that the processing flow can be more regular and extra time for norm-calculation can be excluded. This design was synthesized and layout where the post layout estimation results have shown that the processing throughput of the proposed SQR architecture can out-perform the state of the art by 44.8%.

Table of Contents
摘要		IV
Abstract		V
誌謝		VI
Table of Contents		VII
Figures		IX
Tables		XI
I. Introduction	1
1.1 Background	1
1.2 Previous works	2
1.3 This work’s feature	3
II. MIMO SYSTEM AND SORTED QR-DECOMPOSITION	4
III. GIVENS ROTATION AND CORDIC ALGORITHM	8
3.1 Givens Rotation algorithm	8
3.2	CORDIC Operations	10
3.3 Multi-dimension CORDIC	11
IV. THE PROPOSED SORTED QRD ARCHITECTURE	14
4.1 The Proposed Norm Computation Method	14
4.2 The Architectural overview of the SQR Processor	15
V. THE DETAILED CIRCUIT ARCHITECTURE	19
5.1 The Circuit Structure of the PU_Vec and PU_Rot Units	19
5.2 The Circuits of the CORDIC Processing Elements	21
5.3 The Circuit Architecture of the Min_Norm Units	25
5.4 The Optimization of Critical Path	26
VI.	EXPERIMENTAL RESULTS AND COMPARISONS	30
6.1 Timing and Complexity Analyses	30
6.2 Experimental Results	32
6.3 Comparisons with Prior Arts	34
VII. Conclusion	36
References	37

                                

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