簡易檢索 / 詳目顯示
| 研究生： |
許柏仁 Po-Jen Hsu |
|---|---|
| 論文名稱： |
基於NOC多核心平台之大型MIMO偵測系統架構設計與實現 The Design of A Large-Scale MIMO Detection System on The NOC Based Multicore Platform |
| 指導教授： |
沈中安
Chung-An Shen |
| 口試委員: |
林淵翔
Yuan-Hsiang Lin 吳晉賢 Chin-Hsien W |
| 學位類別： |
碩士 Master |
| 系所名稱： |
電資學院 - 電子工程系 Department of Electronic and Computer Engineering |
| 論文出版年： | 2015 |
| 畢業學年度： | 103 |
| 語文別： | 英文 |
| 論文頁數： | 54 |
| 中文關鍵詞： | 大規模多輸入多輸出 、多輸入多輸出偵測器 、晶片網路 、可程式邏輯 |
| 外文關鍵詞： | Massive MIMO, MIMO detection, Multicore, FPGA. |
| 相關次數： | 點閱：236 下載：9 |
| 分享至: |
| 查詢本校圖書館目錄 查詢臺灣博碩士論文知識加值系統 勘誤回報 |
使用多根發送天線與多根接收天線之多輸入多輸出(Multiple-Input Multiple-Output, MIMO)無線通訊技術已被廣泛認可為可提高資料傳輸速率的最有效方法之一。近年來，使用大量天線的大型MIMO (Massive MIMO) 系統被廣泛討論，使其成為第五代無線通訊系統(5G)的關鍵技術之一。在MIMO系統中，訊號偵測(Signal Detection)是最重要且運算量最龐大的元件之一。而由於其運算複雜度將隨著天線數上升，因此將成為Massive MIMO系統中決定運算時間及複雜度的重大挑戰。此外，隨著無線通訊系統的多樣性的不斷擴展，在未來的Massive MIMO技術中，對於系統彈性的要求將不斷提升，以針對不同應用進行相對應的資源配置。
在另一方面，多核心架構已於各個領域廣泛應用以提升系統效能及處理速度。其中，晶片網路(Network-on-Chip ; NOC)是一個在多核心架構各運算核心間有效率傳遞資料的技術。因此，基於NOC之多核心平台將是能夠達到高運算能力及系統彈性的有效架構。本論文基於NOC多核心平台提出了一套應用於Massive MIMO環境的訊號偵測系統。首先，本論文改進基於樹狀搜尋的MIMO偵測演算法，使其能夠運行於NOC多核心平台。本論文並且詳細描述平台整體超大型積體電路架構、運算單元、及路由器等基本元件。另外在晶片網路中，此論文使用兩種不同網路拓樸，來分析處理效能和系統複雜度之間的取捨。
最後，本論文將顯示此多輸入多輸出偵測器設計適合使用大量天線且可調整的Massive MIMO通訊系統上，另外此論文將展示出基於可程式邏輯(FPGA)開發版的實現結果及效能分析。
In massive MIMO systems, the number of antennas becomes enormous and would need to be configurable in order to support different applications. This brings great challenges in designing efficient MIMO detector structures.
On the other hand, multicore systems have been widely utilized for achieving high processing throughput and the Network-on-Chip (NoC) paradigm has been recognized an effective means of inter-connecting processing elements in the multicore architecture. This thesis explores the design of MIMO detector for massive MIMO systems based on a multicore system using NoC architectures. First of all, a tree-searching based MIMO detection algorithm is revised to be implemented on the NoC-based multicore processor. The VLSI architecture for the processing elements, routers, and thus the entire NoC structure will be clearly depicted. Moreover, two types of NoC topologies are investigated in order to illustrate the design trade-offs between processing speed and system complexity.
In addition, we will show that the proposed MIMO detector engine is suitable for massive MIMO system that equips with large number of antennas and requires a supporting to the configurability. The FPGA implementation for the proposed NoC-based MIMO detector is presented and experimental results are documented.
E. G. Larsson, F. Tufvesson, O. Edfors, and T. L. Marzetta, “Massive MIMO for next generation wireless systems,” IEEE Communications Magazine, vol. 52, no. 2, pp. 186-195, Feb. 2014.
F. Rusek, D. Persson, B. K. Lau, E. G. Larsson, T. L. Marzetta, E. O, and F. Tufvesson, “ Scaling up MIMO: Opportunities and Challenges with Very Large Arrays,” IEEE Signal Proces. Magazine, vol. 30, no. 1, pp. 40-46, Jan. 2013.
G. L. Stüber, J. R. Barry, S. W. Mclaughlin, Y. Li, M. A. Ingram, and T. G. Pratt, “Broadband MIMO-OFDM wireless communications,” IEEE Proceedings, vol. 92, No. 2, pp. 271-294, Feb. 2004.
A. Burg, M. Borgmann, M. Wenk, M. Zellweger, W. Fichtner, and H. Bolcskei, “VLSI implementation of MIMO detection using the sphere decoding algorithm,” IEEE Journal of Solid-State Circuits, vol. 40, pp. 1566-1577, July 2005.
T.-H. Kim and I.-C. Park, “Small-area and low-energy K-best MIMO detector using relaxed tree expansion and early forwarding,” IEEE Trans. Circuits and Systems I: Regular Papers, vol. 57, no. 10, pp. 2753-2761, Oct. 2010.
M.-T. Shiue, S.-S. Long, C.-K. Jao, and S.-K. Lin, “Design and Implementation of Power-Efficient K-Best MIMO Detector for Configurable Antennas,” IEEE Trans. Very Large Scale Integration (VLSI) Systems, vol. 22, no. 11, pp. 2418-2422, Nov. 2014.
M. Wu, S. Gupta, Y. Sun, and J. R. Cavallaro,“A GPU implementation of a real-time MIMO detector,” in Proc. IEEE Workshop on Signal Processing Systems, pp. 303-308, Oct. 2009.
A. M. A. Hussien, R. Amin, A. M. Eltawil, J. Martin, "Energy Aware Mapping for Reconfigurable Wireless MPSoCs," IEEE Trans. VLSI Systems, vol.23, no.2, pp. 392-396, Feb. 2015.
D. F. Macedo, D. Guedes, L. F. M. Vieira, M. A. M. Vieira, M. Nogueira, "Programmable Networks—From Software-Defined Radio to Software-Defined Networking," IEEE Communications Surveys & Tutorials, vol.17, no.2, pp.1102-1125, 2nd quarter 2015.
B. D. De Dinechin, D. van Amstel, M. Poulhies, and G. Lager, "Time critical computing on a single-chip massively parallel processor," Design, Automation and Test in Europe Conference and Exhibition (DATE), pp.1-6 2014.
L. J. Karam, I. AlKamal, A. Gatherer, G. A. Frantz, D. V. Anderson, and B. L. Evans, “Trends in multicore DSP platforms,” IEEE Signal Proces. Magazine, vol. 26, no. 6, pp.38-49, Nov. 2009.
G. Blake, R. G. Dreslinski, and T. Mudge, “A survey of multicore architectures,” IEEE Signal Proces. Magazine, vol. 26, no. 6, pp.26 -37, Nov. 2009.
E. Salminen, V. Lahtinen, K. Kuusilinna, and T. Hamalainen, “Overview of bus-based system-on-chip interconnections,” in Proc. IEEE International Symposium on Circuits and System, vol. 2, pp. 372-375,May 2002.
L. Benini and G. De Micheli, “Networks on Chips: A New SoC Paradigm,” IEEE Computers, vol. 35, no. 1, pp. 70-78, Jan. 2002.
S. Kumar, A. Jantsch, M. Millberg, J. Berg, J. Soininen, M. Forsell, K. Tiensyrj, and A. Hemani, “A network on chip architecture and design methodology,” in Proc. IEEE Computer Society Annual Symposium on VLSI, pp. 105-112, Apr. 2002.
J.H. Rutgers, M. J.G. Bekooij, and G. J.M. Smit, “Evaluation of a Connectionless NoC for a RealTime Distributed Shared Memory Many-Core System,” in Proc. IEEE Digital System Design, pp.727 -730, Sept. 2012.
C. Nicopoulos, V. Narayanan, and C. R. Das, “A Baseline NoC Architecture,” in Network-on-Chip Architectures, 1st ed., Springer Netherlands, 2010, Ch. 2, pp. 13-16.
G. Jiang, Z. Li, F. Wang, S. Wei, "Mapping of Embedded Applications on Hybrid Networks-on-Chip with Multiple Switching Mechanisms," IEEE Embedded Systems Letters, vol.7, no.2, pp. 59-62, Jun. 2015.
T. Majumder, M. E. Borgens, P. P. Pande, and A.Kalyanaraman, "On-Chip Network-Enabled Multicore Platforms Targeting Maximum Likelihood Phylogeny Reconstruction," IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems, vol.31, no.7, pp.1061,1073, July 2012.
X. Ling, Y. Chen, Z. Yu, S. Chen, X. Wang, and G. Liang, "MACRON: The NoC-Based Many-Core Parallel Processing Platform and Its Applications in 4G Communication Systems," in Proc. Euromicro International Conference on Parallel, Distributed and Network-Based Processing (PDP), pp.396-403, Mar. 2015.
M. Martina, and G. Masera, "Turbo NOC: A Framework for the Design of Network-on-Chip-Based Turbo Decoder Architectures," IEEE Trans. Circuits and Systems I: Regular Papers, vol.57, no.10, pp.2776-2789, Oct. 2010.
Q. Yang, X. Zhou, G. E. Sobelman, and X. Li, "Network-on-Chip for Turbo Decoders," IEEE Trans. VLSI Systems, [on-line publication], Feb. 2015.
J. Duato, S. Yalamanchili, and L. Ni, “Message Switching Layer,” in Interconnection Networks: An Engineering Approach, 1st ed., Morgan Kaufmann, 2002, Ch. 2, pp. 43-81.
R. Pau and N. Manjikian,“Implementation of a configurable router for embedded network-on-chip support in FPGAs,” in Proc. IEEE Northeast Workshop on Circuits and Systems and TAISA Conference, pp. 25-28 ,June 2008.
H. V. Thang and P. N. Nam, “Prototyping of a Network-on-Chip on Spartan 3E FPGA,” in Proc. IEEE Second International Conference on Communications and Electronics, pp. 24-28, Oct. 2010.
M. Dehyadgari, M. Nickray, A. Afzali-kusha, and Z. Navabi, “Evaluation of pseudo adaptive XY routing using an object oriented model for NOC,” in Proc. IEEE International Conference on Microelectronics, Dec. 2005.
E. S. Shin, V. J. Mooney, and G. F. Riley, “Round-robin Arbiter Design and Generation,” in Proc. IEEE System Synthesis International Symposium, pp. 243-248, Oct. 2002.
