快閃記憶體為具有低功耗、可擴充性、高效能等優點的非揮發性記憶體，使其成為消費性電子產品中常見的儲存元件，像是固態硬碟、手機和筆記型電腦等產品。快閃記憶體的儲存方式是將電子儲存至浮閘中，隨著製程的進步，由單階儲存細胞 (Single-level Cell, SLC) 衍生出多階儲存細胞 (Multi-level Cell, MLC) 與三階儲存細胞 (Triple-level Cell, TLC)，快閃記憶體的儲存密度不斷的提升，但同時也使記憶體細胞的雜訊邊界縮小，進而導致記憶體可靠度與耐久度的下降。而內建自我修復技術是常見的錯誤修正方式，但過去研究中提出的備用元件較不細緻，導致修復率、良率和可靠度皆無法有效提升。
因此，本論文提出細內建自我修復技術來解決這些問題，也提出本論文定義的故障模型，結合過去的故障模型並加以分類，而將過去較不細緻的備用元件，分成備用字、備用頁、備用行和備用非及型區塊四種備用元件來使用，利用提出的演算法將分類好的故障模型和配置的備用元件做合適的對應，以備用元件取代故障細胞，來有效地完成修復。
本篇研究實現了細內建自我修復技術的電路，並於1 GB之快閃記憶體上進行修復率、良率、可靠度和硬體成本分析。實驗結果顯示記憶體大小在1 GB，每個區塊平均瑕疵數目設為10，且位元可修復錯誤比率為0.8、頁可修復錯誤比率為0.1、行可修復故障比率為0.05、非及型區塊可修復故障比率為0.05時，每個區塊的備用元件總數為四個備用非及型區塊以及兩個備用行情況下，修復率可維持在 98% 以上，良率也仍可維持在 99% 以上，而在經過 1.5×106小時後仍可維持達0.9之可靠度，在條件相同下與粗內建自我修復技術比較，可接受可靠度若訂在0.9，約可延長2.7倍的使用壽命。

Flash memory is a non-volatile memory with the advantages of low power consumption, good scalability, and high performance, making it a common storage component in consumer electronic products, such as solid-state drives, mobile phones, and laptops. The storage method of flash memory is to store electrons in the floating gate. As the process progresses, multi-level cells (MLC) and triple-level cell (TLC) are derived from single-level cells (SLC), the storage density of flash memory continues to increase, but it also reduces reliability margin of the memory cells, which leads to decrease in memory reliability and endurance. The built-in self-repair techniques and error correction codes are the common fault tolerance techniques, but the spare elements proposed in the conventional research are coarse, resulting in the failure to improving the repair rate, yield, and reliability.
Therefore, we propose the fine-grained BISR (FGBISR) techniques to replace the conventional CGBISR techniques. Fine-grained spare units such as spare words, spare pages, spare columns, and spare NAND blocks can be used. Based on the fault behaviors and the conventional flash memory fault models, more sophisticated fault models are defined. Novel redundancy analysis algorithm is derived based on the new fault types
In this work, a circuit with FGBISR techniques is implemented, and repair rate, yield, reliability, and hardware overhead analysis are performed on a 1 GB flash memory. Experimental results show that when the average number of defects per block is set to 10, and the bit-repairable fault rate is 0.8, the page repairable fault rate is 0.1, the page repairable fault rate is 0.05, and the NAND block repairable failure ratio is 0.05, When the amount of spare components equal to four spare NAND blocks and two spare columns per block, the repair rate can be maintained above 98%, the yield can still be maintained above 99%. Reliability is 0.9 after 1.5×106 hours of use. Under the same conditions, compared with the CGBISR techniques. If the acceptable reliability is set at 0.9, the lifetime can be extended by about 2.7 times.

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