傳統記憶體如DRAM與快閃記憶體，皆以儲存電荷的方式儲存資料，但此種方式在微縮製程上遇到了瓶頸，例如電荷量的限制。因此近年來，多種電阻式記憶體被提出，其中相變化記憶體最受關注，其原理是利用材料在不同狀態下具有不同的電阻值來儲存資料，並具有高可擴展性、非揮發性、快速存取、數據保存能力強、低成本與低耗電等優點。然而，相變化記憶體的最大缺點在於寫入次數的限制，當相變化記憶體細胞的寫入次數達到 〖10〗^7 ~ 〖10〗^8 次時，加熱元件與相變化材料可能會分離，而導致永久性的固定型故障。
使用錯誤修正碼是很常見的修復故障的方法，過去的技術皆為每筆資料都配上錯誤修正碼保護，但因為相變化記憶體的永久性錯誤是慢慢出現並且逐步累積，故一開始便將所有資料配置錯誤修正碼將會浪費許多儲存空間。因此本篇論文提出適應性編碼技術，其核心概念為記憶體列出現故障後再配置檢驗碼單元 (Check-Bit Entry)。初始時每列資料只配置一位元的奇偶校驗位元，在故障出現時，奇偶校驗位元即能將之偵測出來，接著利用硬錯誤修正技術修復故障，並將該錯誤列配置錯誤修正碼。本研究使用的錯誤修正碼是單錯誤修正與雙錯誤偵測的修正漢明碼，當另一個故障出現時，錯誤修正碼能偵測出有兩個錯誤，然後利用硬錯誤修正技術修復錯誤，並且將該記憶體區塊做列拌碼 (Row Scrambling) 處理，讓每列資料最多只有一個錯誤，而且每個故障列皆配置檢驗碼單元。此外，本研究依照儲存檢驗碼單元的ECC DRAM與相變化記憶體之對映關係提出了兩種架構：局部適應性編碼技術與全域適應性編碼技術。
經過硬體成本公式計算，本研究所提出的技術量相較於一般全配修正漢明碼的方式，至少減少70 % 的額外電晶體數，並且發展一個模擬器以評估修復率，在沒有使用列拌碼分散故障的錯誤情況下，本技術之修復率僅略低於全配修正漢明碼，而可靠度經過公式計算，也與全配修正漢明碼差異不大。

Traditional memories such as DRAM and flash memory represent information as the presence or absence of electric charges. However, they pose a threat to scaling due to physical limitations. Therefore, in recent years, a variety of resistive memories have been proposed. Among these emerging technologies, phase change memory (PCM) has received the most research attentions because it has the advantages of high scalability, non-volatility, fast access, strong data retention, low cost, and low power consumption. PCM encodes bits with different physical states of the chalcogenide material. The major disadvantage of PCM is its limited write endurance. As writing data into PCM for 〖10〗^7 ~ 〖10〗^8 times, the heating element may be separated from the phase change material. Finally, it will result in a stuck-at failure.
Using error correction code (ECC) to repair faults is a popularly used technique in the past. That is, each data word is equipped with check bits for correcting errors. However, the probability of occurring permanent faults is low and soft errors are not a main threat for PCM, equipping ECC for each data word will waste a lot of storage space. Therefore, this thesis proposes adaptive coding techniques to cure the drawback of the conventional ECC techniques. The main idea is to allocate check-bit entries merely for faulty rows. In the beginning, every PCM row is equipped with a parity bit. It can be used to detect the first faluty bit occurring in the PCM row. This faulty bit than can be repaired with the hard error correction technique. Thereafter, a check-bit entry is allocated for the the faulty row. The adopted ECC in this thesis is the modified Hamming code which can correct a single error and detect double errors. When another fault appears, the modified Hamming code can detect it and then repair this fault by the hard error correction technique. We can then execute the row scrambling technique for the PCM block containing this faulty row. The goal of scrambling is to make each row containing at most one faulty bit such that the adopted ECC can correct them successfully. Furthermore, this thesis proposes two ways of adaptive codingthe local adaptive coding technique and the global adaptive coding technique, based on the usability of the incorporated check-bit entries in the ECC DRAM.
Hardware model is derived for evaluating the hardware overhead. According to evaluation results, the extra transistor count of the proposed adaptive coding techniques is at least 70% lower than the original ECC technique. A simulator is also developed for estimating the repair rate. Experimental results show that, the repair rate and reliability of the adaptive coding techniques are only slightly lower than the original ECC technique without using the row scrambling.

[1] Semico Res. Corp., 2007. https://semico.com/content/semico-systems-chip -%E2%80%93-braver-new-world
[2] Int’l Technology Roadmap for Semiconductors (ITRS), Emerging Research Devices, 2009.
[3] K. Kim, “Technology for sub-50 nm DRAM and NAND flash manufacturing,” in Proc. Annu. IEEE Int’l Electron Devices Meeting (IEDM), vol. 5, pp. 323-326, Dec. 2005.
[4] B. C. Lee, E. Ipek, O. Mutlu, and D. Burger, “Architecting phase change memory as a scalable DRAM alternative,” in Proc. 36th Int’l Symp. on Comput. Architecture (ISCA ’09), pp. 2-13, June, 2009.
[5] P. Zhou, B. Zhao, J. Yang, and Y. Zhang, “A durable and energy efficient main memory using phase change memory technology,” in Proc. 36th Int’l Symp. on Comput. Architecture (ISCA ’09), pp. 14-23, June, 2009.
[6] N. H. Seong, D. H. Woo, and H. S. Lee, “Security refresh: prevent malicious wear-out and increase durability for phase-change memory with dynamically randomized address mapping,” in Proc. 37th Int’l Symp. on Comput. Architecture (ISCA ’10), pp. 383-394, 2010.
[7] P. Zhou, B. Zhao, J. Yang, and Y. Zhang, “A durable and energy efficient main memory using phase change memory technology,” in Proc. 36th Int’l Symp. on Comput. Architecture (ISCA ’09), pp. 14-23, June, 2009.
[8] M. K. Qureshi, J. Karidis, M. Franceschini, V. Srinivasan, L. Lastras, and B. Abali, “Enhancing lifetime and security of pcm-based main memory with start-gap wear leveling,” in Proc. 42nd IEEE/ACM Int’l Symp. on Microarchitecture, pp. 14-23, Dec. 2009.
[9] F. Huang, D. Feng, W. Xia, W. Zhou, Y. Zhang, M. Fu, C. Jiang, and Y. Zhou, “Security RBSG: Protecting Phase Change Memory with Security-Level Adjustable Dynamic Mapping,” in Proc. Int’l Parallel and Distributed Processing Symp. (IPDPS), pp. 1081-1090, May 2016
[10] J. Yun, S. Lee, and S. Yoo, “Dynamic Wear Leveling for Phase-Change Memories With Endurance Variations,” IEEE Trans. Very Large Scale Integration (VLSI) Systems, vol. 23, no. 9, pp. 1604-1615, Sep. 2015.
[11] B. D. Yang, J. E. Lee, J. S. Kim, J. Cho, S. Y. Lee, and B. G. Yu., “A low power phase-change random access memory using a data-comparison write scheme,” in Proc. IEEE Int’l Symp. on Circuit and Systems, pp. 3014-3017, May 2007.
[12] S. Cho and H. Lee, “Flip-n-write: a simple deterministic technique to improve PRAM write performance, energy and endurance,” in Proc. Int’l Symp. on Microarchitecture (MICRO), pp. 347-357, Dec. 2009.
[13] C. Chen, and J. An, “DRAM write-only-cache for improving lifetime of phase change memory,” in Proc. 59th Int’l Midwest Symp. on Circuits and Systems (MWSCAS), pp. 1-4, Oct. 2016.
[14] A. P. Ferreira, M. Zhou, S. Bock, B. Childers, R. Melhem, and D. Mosse, “Increasing PCM main memory lifetime,” in Proc. Design, Autom. Test Eur. Conf. Exhibit. (DATE), pp. 914-919, Mar. 2010.
[15] G. Wu, J. Gao, H. Zhang, and Y. Dong, “Improving PCM endurance with randomized address remapping in hybrid memory system,” in Proc. IEEE Int’l Conf. Cluster Computing, pp. 503-507, Sep. 2011.
[16] G. Wu, H. Zhang, Y. Dong, and J. Hu, “CAR: Securing PCM main memory system with cache address remapping,” in Proc. IEEE Int’l Conf. Parallel and Distributed Systems, pp. 628-635, Dec. 2012.
[17] E. Ipek, J. Condit, E. Nightingale, D. Burger, and T. Moscibroda. “Dynamically replicated memory: Building resilient systems from unreliable nanoscale memories,” in Proc. 55th Int’l Conf. on Architectural Support for Programming Languages and Operating Systems (ASPLOS) , pp. 3-14, Mar. 2010.
[18] S. Schechter, G. H. Loh, K. Strauss, and D. Burger, “Use ECP, not ECC, for hard failures in resistive memories,” in Proc. Int’l Symp. Comput. Architecture, pp. 141-152, 2010.
[19] N. H. Seong, D. H. Woo, V. Srinivasan, J. Rivers, and H. H. Lee, “SAFER: Stuck-at-fault error recovery for memories,” in Proc. 43rd IEEE/ACM Int’l Symp. on Microarchitecture (MICRO), pp. 115-124, Dec. 2010.
[20] L. Jiang, Y. Du, Y. Zhang, B. R. Childers, and J. Yang, “LLS: Cooperative integration of wear-leveling and salvaging for pcm main memory,” in Proc. 41st IEEE/IFIP Int’l Conf. on Dependable Systems and Networks (DSN), pp. 221-232, June 2011.
[21] D. H. Yoon, N. Muralimanohar, J. Chang, P. Ranganathan, N. P. Jouppi, and M. Erez, “FREE-p: Protecting non-volatile memory against both hard and soft errors,” in Proc. 17th IEEE Int’l Symp. on High Performance Computer Architecture (HPCA), pp. 466-477, Feb. 2011 .
[22] R. Melhem, R. Maddah, and S. Cho, “RDIS: A recursively defined invertible set scheme to tolerate multiple stuck-at faults in resistive memory,” in Proc. 42nd IEEE/IFIP Int’l Conf. on Dependable Systems and Networks (DSN), pp. 1-12, June 2012.
[23] S. K. Lu, C. J. Tsai, and M. Hashizume, “Enhanced built-in self-repair techniques for improving fabrication yield and reliability of embedded memories,” IEEE Trans. Very Large Scale Integration (VLSI) Systems, vol. 24, no. 8, pp. 2726-2734, Aug. 2016.
[24] M. G. Mohammad, “Fault model and test procedure for phase change memory,” IET Comput. Dig. Tech., vol. 5, no. 4, pp. 263-270, July 2011.
[25] B. C. Lee, P. Zhou, J. Yang, Y. Zhang, B. Zhao, E. Ipek, O. Mutlu, and D. Burger, “Phase-change technology and the future of main memory,” IEEE Micro, vol. 30, no. 1, pp. 131–141, 2010.
[26] L. Shi, R. Zhao, and T. C. Chong, “Phase-change random access memory,” IEEE, Developments in Data Storage: Materials Perspective, pp. 277-296, 2012.
[27] K. Pagiamtzis and A. Sheikholeslami, “Content-addressable memory (CAM) circuits and architectures: A tutorial and survey,” IEEE J. Solid-State Circuits, vol. 41, no. 3, pp. 712–727, Mar. 2006.