本篇論文提出適用於適合於生醫應用之可編程多通道類比感測前端低功耗積體電路，每一通道包含生理感測放大器、可變增益放大器及高線性度轉導電容濾波器，不同類比感測通道之類比輸出利用一逐漸趨近式類比至數位轉換器轉換為數位訊號，其中之感測電路利用懸浮閘電晶體及其相關之類比編程技術使感測類比前端電路達到低功耗、低雜訊及可編程之特性；並使用串並列輸出介面電路傳輸所有懸浮閘編程及校正所需之控制訊號以節省所需之晶片腳位，且所設計之類比感測前端電路可以依據使用者需求選擇不同的訊號處理路徑。此外，模組化之佈局方式可於未來需要整合更多類比感測通道時，可輕易擴增系統晶片之通道數，減少整合所需之時間。
本論文所設計之電路利用台積電0.35m標準CMOS製程設計並製作一四通道之類比前端感測晶片，其中並整合懸浮閘電晶體所需之編程電路。經量測可知，當類比感測電路之頻寬設定為100Hz時，所消耗之電流為50nA，等效輸入雜訊為2.85 ，計算所得之雜訊效能因數為2.48，動態範圍為46.24dB。當頻寬增加至1KHz時，所消耗之電流為634nA，等效輸入雜訊為3.03 ，計算所得之雜訊效能因數為2.98，動態範圍為46.33dB；量測所得之類比數位轉換器有效位元數為5.9Bits，最後並以心電訊號模擬器驗証晶片之功能。

This thesis presentslow-power integrated circuit design of a reconfigurable multi-channel analog sensing front end for biomedical applications. Each single channel consists of a biopotential sensing amplifier(LNA), a variable gain amplifier (VGA), and a linearized operationaltransconductance amplifier-capacitor(OTA-C) filter. The analog output signals from different channels are converted into digital format viaasuccessive approximationregisteranalog to digital converter(SAR ADC).By employingfloating-gate transistors and the relevant analog programming techniques, the analog sensing front-end circuits achieve features of low power, low noise and reconfigurability. Besides, to save the number of chip pins, serial-peripheral interface circuits are used to transmit the controls signals required for floating-gate programming and circuit calibration. The signal path can also be adjusted according to the demands of users. Moreover, the circuit layout are modulized so that the number of the sensing channels can be extended easily in the future.
The integrated circuits presented in this these have been designed and fabricated in a TSMC 0.35mstandard CMOS process. The chip includes four channel analog sensing front-end and the circuits for floating-gate programming. From the measurements, when the bandwidth is programmed at 100Hz, the total current consumption for single channel is 50nA with input referred noise of 2.85 . The calculated noise efficiency factor (NEF) is 2.48 and the dynamic range is 46.24dB. When the bandwidth is increased to 1kHz, the current consumption becomes 634nA with input referred noise of 3.03 and NEF of 2.98 and dynamic range is 46.33dB. The measured number of effective bits from the employed SAR ADC is 5.9. Finally, the functionality of the chip is verified by a signal from an ECG simulator.

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