本篇論文應用懸浮閘編程技術提出提出兩個可適用於穿戴式生理訊號感測裝置或物聯網系統之可重組化低功耗不需離散電容穩壓器。兩個穩壓器電路都使用懸浮閘nMOS 導通電晶體與自適性AB 類放大器，並利用電容性電路建立參考電壓並進行電壓回授。由於使用懸浮閘nMOS 導通電晶體，所提出之穩壓器較一般採用pMOS 導通電晶體之穩壓器擁有更優異的電源雜訊抑制能力，並保有低壓降的特性；此外，採用了自適性AB 類放大器，可降低靜態功耗並提升穩壓器暫態反應速度；所提出之穩壓器電路採用電容性電路建立參考電壓並進行電壓回授，可節省傳統之能隙參考電壓電路及電阻分壓電路之功耗，量測所得之輸出電壓溫度係數可小於45 ppm/◦C，此外可藉由調整懸浮閘上的電荷，輸出電壓可適需求連性編程。
論文中所提出之第一個穩壓器電路提供穩定電壓給低功耗類比前端感測電路使用，輸出電壓範圍為1.2V 至2.5V，由於負載電流並不會劇烈變動，因此設計之重點為電源抑制能力與低功耗。晶片之靜態電流小於1A可量測得到75 dB的電源雜訊抑制能力，可達到的電流效率高於99.9%，在沒有負載下穩壓器的最大負載電容可以達到1nF。
論文中所提出之第二個穩壓器為提供電壓給低功耗之數位電路。除了承襲了第一個穩壓器的優點，並進一步改善原本電路所受限之最低輸出電壓及負載暫態反應速度。所提出的穩壓器採用了摺疊差動對所建構之自適性AB 類誤差放大器，使放大器所需之最低電壓得以降低至0.9V；為了應付數位電路負載電流的快速變化，論文中也提出一無靜態功耗之負載暫態增進電路，並為了防止電路於啟動階段消耗過多電流設計一電源啟動重置電路。穩壓器之最大負載電流設計為2 mA，靜態電流小於1 A，可達到的電流效率高於99.95%。根據模擬結果，線性調節率為0.056mV/V 或85.1dB 的電源雜訊抑制能力。藉由採用暫態提升電路，可使本穩壓器的壓降回復時間縮短至2.7u s。第二個穩壓器在沒有負載的情況下最大負載電容可以達到100pF。

Two reconfigurable power-efficient high-performance output-capacitor-less (OCL)linear voltage regulators are proposed in this thesis. These low-drop-out (LDO) voltage regulators are designed for wearable devices in biomedical or internet of things (IoT) applications. Both regulators employ floating-gate programming technologies to achieve reconfigurability and low power consumption. These regulators adopt a floating-gate nMOS pass transistor, an adaptively biased error amplifier, and capacitive circuits for voltage reference generation and for feedback sensing. With a floating-gate nMOS pass transistor, the proposed regulators exhibit superior line regulation to conventional regulators that usually employ a pMOS pass transistor. The error amplifier adopts a class-AB input differential pair and an adaptively biased regulated cascode topology to improve transient response under the stringent constraint of low quiescent current consumption. The reference voltage is implemented by programming charges on capacitors without employing a bandgap circuit. As a result, the power consumption for bandgap reference circuit can be saved. The measured output voltage temperature coefficient can be lower than 45 ppm/◦C. By programming charges in floating-gate transistors, the regulated output voltage can be adjusted in continuum depending on the applications.
The proposed first regulator is designed for low-power analog sensing front-end circuits. The designed output voltage ranges from 1.2V to 2.5V and the designed maximum load current is 1mA with output voltage drop less than 0.1%. Since the load current does not change dramatically, the design focus is on line regulation rather on load regulation. A prototype chip is designed and fabricated in a 0.35um CMOS process to demonstrate the reconfigurability and to validate the performance. With programmable quiescent current levels less than 1 A, the current efficiency is higher than 99.9%. From measurements, the line regulation is 0.17mV/V or 75dB. The designed output-capacitor-less regulator remains stable with maximum output load capacitance upto 1nF under the zero load condition.
The second regulator is designed for low-power digital circuits. To cope with the dramatic changes of the load current and reduced output voltage, the second regulator improves the required minimum supply voltage of the error amplifier and employs a load transient enhancement circuit that consumes no static power. To prevent huge current consumption
during the circuit start-up phase, a power-on-reset (POR) circuit is designed and verified. A folded-class-AB differential pair circuit is employed to reduce the required error amplifier minimum supply voltage to 0.9V. The maximum load current is designed to be 2mA. With programmable quiescent current levels less than 1 A, the current efficiency is higher than 99.95%. From simulations, the line regulation is 0.056mV/V or
?85.1dB. By using the load transient enhancement circuit the undershoot settling time of the LDO is reduced to 2.7u s. The designed OCL LDO remains stable with maximum output load capacitance upto 100pF under the zero load condition.

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