在無線通訊收發機中，鎖相迴路是用於實現頻率及相位的同步技術。在鎖相迴路裡面，包含頻率相位偵測器、充電幫浦、迴路濾波器、電壓控制震盪器、除頻器是主要組成的核心電路，我們主要的研究方向是電壓控制震盪器及除頻器，這兩塊核心電路最具影響鎖相迴路效能，目標要達到低功耗、低相位雜訊、有較寬的工作頻率範圍。
第一部分，呈現一個C類交叉對共振腔震盪器，實現寬頻注入鎖定除頻器，可以用於除2及除4的除頻器，此除頻器使用台積電0.18微米製程，晶片面積為1.1496 * 1.089 mm2。此電路包含由兩個N型金氧半電晶體交錯耦合對為中心所組成的電壓控制震盪器，以及一個用來注入訊號的N型金氧半電晶體並聯共振腔三個電感所組成。除4除頻器為工作電壓操作在1.1伏特，整體功耗為10.6 mW，在注入強度為0 dBm時，除頻範圍可從8.03 GHz ~ 11.56 GHz，百分比為36.04 %。除2除頻器為工作電壓操作在1.05伏特，整體功耗為8.01 mW，在注入強度為0 dBm時，除頻範圍可從1.72 GHz ~ 7.51 GHz，百分比為125.46 %。
第二部分，呈現一個C類交叉對共振腔震盪器，實現寬頻注入鎖定除頻器，可以用於除2及除4的除頻器，此除頻器使用台積電0.18微米製程，晶片面積為0.5593 * 0.976 mm2。此電路包含由兩個N型金氧半電晶體交錯耦合對為中心所組成的電壓控制震盪器，以及一個用來注入訊號的N型金氧半電晶體並聯共振腔兩個電感所組成。除4除頻器為工作電壓操作在1伏特，整體功耗為6.62 mW，在注入強度為0 dBm時，除頻範圍可從14.4 GHz ~ 16.94 GHz，百分比為16.21 %。除2除頻器為工作電壓操作在0.8伏特，整體功耗為4.07 mW，在注入強度為0 dBm時，除頻範圍可從3.6 GHz ~ 10.1 GHz，百分比為94.891 %。
最後，呈現一個C類交叉對共振腔震盪器，實現寬頻注入鎖定除奇數除頻器，此除頻器使用台積電矽鍺0.18微米製程，晶片面積為0.817 * 1.176 mm2。此電路包含由兩個N型金氧半電晶體交錯耦合對為中心所組成的電壓控制震盪器，以及一組雙注入訊號的N型金氧半電晶體並聯共振腔三個電感、兩個電阻、兩個電容所組成。工作電壓操作在0.9伏特，整體功耗為7.58 mW，在注入強度為0 dBm時，除5的除頻範圍可從11.2 GHz ~ 14.4 GHz，百分比為25.26 %；除3的除頻範圍可從5.73 GHz ~ 10.02 GHz，百分比為54.47 %；除1的除頻範圍可從1.63 GHz ~ 3.36 GHz，百分比為69.34 %。

In a RF transceiver of the wireless communication system, PLL keep the input and output phase in lock step also implies keeping the input and output frequencies the same. PLL, including Phase Frequency Detector (PFD), Charge Pump (CP), Loop Filter (LF), Voltage Controlled Oscillator (VCO), and Frequency Divider (FD), are important circuits. We major in Voltage Controlled Oscillator (VCO) and Frequency Divider (FD). The two parts influence the performance. Low power, low phase noise, and wide operating frequency range are what we focus on goals.
First, a wide locking range LC injection-locked frequency divider (ILFD) using lumped inductor as the resonator. The ILFD was implemented in the TSMC 0.18 μm 1P6M CMOS process and it shows the property of dual-resonance ILFD. The ILFD uses a capacitive cross-coupled voltage-controlled oscillator (VCO) as the core and also uses one direct injection MOSFET. The dc gate bias of cross-coupled FETs is smaller than dc drain bias. The dc gate bias of injection MOSFET is smaller than dc drain/source bias. The ILFD can be used as a divide-by-2 or divide-by-4 ILFD. The die area is 1.1496 × 1.089 mm2. At the drain-source bias of 1.1 V, and at the incident power of 0 dBm the locking range of the divide-by-4 ILFD is 3.53 GHz (36.04%) from 8.03 to 11.56 GHz. The core power consumption is 10.6 mW. At the dc drain-source bias of 1.05 V and at the incident power of 0 dBm the locking range of the divide-by-2 ILFD is 5.79 GHz (125.46％) from 1.72 to 7.51GHz. The core power consumption is 8.01mW.
Secondly, we design a injection-locked frequency divider (ILFD) using a capacitive cross-coupled voltage-controlled oscillator (VCO) with one direct injection MOSFET. The ILFD uses two on-chip inductors in the resonator and has overlapped dual-band locking ranges. The LC ILFD was implemented in the TSMC 0.18 μm 1P6M CMOS process. The dc gate bias of cross-coupled switching FETs is smaller than dc drain bias and is used to tradeoff the locking range and power consumption. The ILFD uses two on-chip inductors. The ILFD can be used as a divide-by-2 or divide-by-4 ILFD. The die area is 0.559 × 0.976 mm2. At the drain-source bias of 1 V, and at the incident power of 0 dBm the locking range of the divide-by-4 ILFD is 2.54 GHz (16.21%) from 14.4 to 16.94 GHz, the percentage is 16.21%. The core power consumption is 6.62 mW. At the drain-source bias of 0.8 V, and at the incident power of 0 dBm the locking range of the divide-by-2 ILFD is 6.5 GHz (94.891%) from 3.6 to 10.1 GHz. The core power consumption is 4.07 mW.
Finally, a wide locking range divide-by-odd number injection-locked frequency divider (ILFD) using a standard 0.18 μm BiCMOS process is presented. The ILFD circuit bases on capacitive cross-coupled oscillator and uses resonator with resistor to enhance the locking range. The power consumption of the ILFD core is 7.58 mW. The divider’s free-running frequency is around 2.5 GHz, and at the incident power of 0 dBm the divide-by-5 locking range is 3.23 GHz (25.26%), from the incident frequency 11.17 to 14.4 GHz; the divide-by-3 locking range is 4.29 GHz (54.47%), from the incident frequency 5.73 to 10.02 GHz; the divide-by-1 locking range is 1.73 GHz (69.34%), from the incident frequency 1.63 to 3.36 GHz.

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