首先，利用台積電零點一八微米製程製作一個新型寬頻串聯共振除三注入鎖定除頻器，此除三注入鎖定除頻器電路利用串聯共振腔和NMOSFET和交叉耦合的振盪器，注入鎖定電晶體作為一倍頻器和動態線性混波器，可以加大鎖頻範圍，功率消耗為10.56 mW，此除頻器的可調範圍為 3.529 GHz到3.828 GHz，在注入0dBm功率時，鎖頻範圍為9.5到11.8GHz，其鎖定範圍大約為2.3GHz (21.6%)，可操作的鎖頻範圍為9.3到11.8GHz ，其鎖定範圍大約為2.5GHz (23.7%)。
其次，實驗熱載子效應對寬頻串聯共振除三注入鎖定除頻器造成RF特性的影響，在注入鎖定除頻器施加高的電壓去刺激RF應力效應，注入鎖定除頻器電流功率消耗會隨著熱應力時間遞減，這是由NMOS交叉耦合轉導衰減造成，注入鎖定除頻器中的注入電晶體的轉導衰減導致電壓擺幅減小，所以造成鎖頻範圍的縮小。
　　最後，研究熱應力效應在除２／除４注入鎖定除頻器所造成的影響，利用台積電點一八製程製作的注入鎖定除頻器，此注入鎖定除頻器利用一個直接注入電晶體去耦合ＬＣ共振腔額外的訊號，結果發現隨著應力時間，鎖頻範圍減少和震盪頻率提高，在未注入和注入的相位雜訊值會隨著應力時間增加而遞增。

First, A new wide locking range series-tuned divide-by-3 injection-locked frequency divider (ILFD) using a standard 0.18 μm CMOS process is presented. The ÷3 ILFD circuit is realized with a series-tuned cross-coupled n-core MOS LC-tank oscillator. Two direct-injection MOSFETs in series are used as a frequency doubler and a dynamic linear mixer to widen the locking range. The core power consumption of the ILFD core is 10.56 mW. The divider’s free-running frequency is tunable from 3.529 GHz to 3.828 GHz by tuning the varactor’s control bias, and at the incident power of 0 dBm the maximum locking range is 2.3 GHz (21.6%), from the incident frequency 9.5 GHz to 11.8 GHz. The operation range is 2.5GHz (23.7%), from 9.3GHz to 11.8 GHz.
Second, investigates the hot carrier effects on the RF characteristics of a series-tuned divide-by-3 injection-locked frequency divider (ILFD). The ÷3 ILFD was implemented in the TSMC 0.18 μm CMOS process. High supply voltage was applied to excite high RF voltage stress on the ILFD. ILFD-core current and power consumptions decrease with stress time, this was attributed to the transconductance degradation of cross-coupled n-core MOS. The locking range degradation is caused by the transconductance degradation of injection MOSFETs and low ILFD voltage swing.
Finally, introduce the Hot carrier (HC) effect on a divide-by-2/-4 injection-locked frequency divider (ILFD). The ILFD was implemented in the TSMC 0.18 μm 1P6M CMOS process. The ILFD uses one direct injection MOSFETs for coupling external signal to the LC resonator. It is shown that the divide-by-2/-4 locking range decreases and the oscillation frequency increases with stress time, and the phase noise in both the free-running and locked state increases with stress time.
 

[1] J. Roggers, C. Plett, Radio frequency integrated circuit design, Artech House, 2003
[2]B. Razavi, RF Microelectronics, Prentice Hall PTR, 1998.
[3]Behzad Razavi Design of Integrated Circuits for Optical Communications, Mc Graw Hill.
[4]林曉彤, 莊惠如, “應用於無線通訊之CMOS 射頻微機電開關及2-GHz/5-GHz 壓控振盪器RFIC之研究” 2004.06.
[5] B. Razavi, Design of Analog CMOS Integrated Crcuits, MC Graw Hall,2001.
[6]P.-C. Huang, M.-D. Tsai, H. Wang, C.-H. Chen, and C.-S. Chang, “A 114GHz VCO in 0.13μm CMOS technology,” IEEE International Solid-State Circuits Conference, vol. 1, pp.404-606, 6-10 Feb. 2005.
[7]P.-C. Huang, M.-D. Tsai, H. Wang, C.-H. Chen, and C.-S. Chang, “A 114GHz VCO in 0.13μm CMOS technology,” IEEE International Solid-State Circuits Conference, vol. 1, pp.404-606, 6-10 Feb. 2005.
[8]S. Smith, “Microelectronic Circuit 4th edition,” Oxford University Press 1998.
[9] J. Craninckx and M. S. J. Steyaert, “A 1.75-GHz/3-V dual-modulus divide-by-128/ 129 prescaler in 0.7 um CMOS,” IEEE J. Solid-State Circuits, vol. 31, pp. 890-897, July 1996.
[10] Q. Huang and R. Rogenmoser, “Speed optimization of edge-triggered CMOS
circuits for gigahertz single-phase clocks,” IEEE J. Solid-State Circuits, vol. 31, pp. 456-463, Mar. 1996.
[11] J. Lee and B. Razavi, “A 40 GHz frequency divider in 0.18-um CMOS
technology,” IEEE J. Solid-State Circuits, vol. 39, pp. 594-601, Apr. 2004.
[12] H. R. Rategh, and T.H. Lee, “Superharmonic injection-locked frequency
dividers,” IEEE J. Solid-State Circuits, vol. 34, pp. 813-821, June 1999.
[13] H. D. Wohlmuth and D. Kehrer, “A high sensitivity static 2:1 frequency divider up to 27 GHz in 120 nm CMOS,” IEEE European Solid State Circuits Conference (ESSCIRC), pp. 823-826, Sept. 2002.
[14] M. Tiebout, “A 480 uW 2 GHz ultra low power dual-modulus prescaler in
0.25 um standard CMOS,” IEEE International Symposium on Circuit and System (ISCAS), vol. 5, pp. 741-744, May 2000.
[15] H. Wu, and A. Hajimiri, “A 19 GHz 0.5 mW 0.35 μm CMOS frequency divider with shunt-peaking locking-range enhancement,” IEEE ISSCC Dig. Tech. Papers, pp. 412-413, Feb. 2001.
[16] R. J. Betancourt-Zamora, S. Verma, and T. H. Lee, “1 GHz and 2.8 GHz CMOS injection- locked ring oscillator prescalers,” IEEE Symposium on VLSI Circuits, pp. 47-50, June 2001.
[17] P. Kinget, R. Melville, D. Long, and V. Gopinathan, “An Injection Locking
Scheme for Precision Quadrature Generation,” IEEE J. Solid-State Circuits, vol. 37, pp. 845-851, July 2002.
[18] W. Z. Chen, and C. L. Kuo, “18 GHz and 7 GHz superharmonic injection-locked dividers in 0.25pm CMOS technology,” IEEE European Solid State Circuits Conference (ESSCIRC), pp. 89-92, Sept. 2002.
[19] H. Wu, “Signal generation and processing in high-frequency/high-speed
silicon-based integrated circuits,” PhD thesis, California Institute of Technology, 2003.
[20]H. Wu and A. Hajimiri, “A 19 GHz 0.5 mW 0.35 μm CMOS frequency divider with shunt-peaking locking-range enhancement,” in IEEE ISSCC Dig. Tech. Papers, Feb. 2001, pp. 412-413.
[21]H. R. Rategh and T. H. Lee, “Superharmonic injection-locked frequency dividers,” IEEE J. Solid-State Circuits, vol. 34, no. 6, pp. 813–821, June 1999.
[22]S.-L. Jang, S.-S. Huang, J.-F. Lee and M.-H. Juang , ” LC-tank Colpitts injection-lockedfrequency divider with record locking range,” IEEE Microw. Wireless Compon. Lett., pp.560-562, Aug. 2008.
[23]Y.-C. Chiang and M.-F. Wu,” A 3.51-to-3.8GHz divide-by-3 injection-locked frequency divider ,” Microw. Opt. Technol. Lett., pp.490-492, Feb., 2010.
[24]S.-L. Jang, Y.-S. Chen, C.-W. Chang, and C.-C. Liu, ” A wide-locking range ÷3 injection-locked frequency divider using linear mixer,” IEEE Microw. Wireless Compon. Lett., vol. 20, pp.390-392, July, 2010.
[25]S.-L. Jang, Y.-S. Chen, C.-W. Chang and C.-C. Liu,” injection-locked frequency dividing apparatus”, US patent # US008305116B2, 2012.
[26]C.-W. Chang, S.-L. Jang, and C.-W. Hsieh,” Wide-locking range ÷3 active-inductor injection-locked frequency divider using the push-push oscillator,” Microw. Opt. Technol. Lett., pp.2771-2773, Dec, 2011.
[27]Y.-T. Chen, M.-W. Li, H.-C. Kuo, T.-H. Huang, and H.-R. Chuang, “Low-voltage k-Band divide-by-3 injection-locked frequency divider with floating-source differential injector,” IEEE Trans. Microw. Theory Tech., vol. 60, no. 1, pp. 160–67, 2012.
[28]Wu and A. Hajimiri, “A 19 GHz 0.5 mW 0.35 μm CMOS frequency divider with shunt-peaking locking-range enhancement,” in IEEE ISSCC Dig. Tech. Papers, Feb. 2001, pp. 412-413.
[29]H. R. Rategh and T. H. Lee, “Superharmonic injection-locked frequency dividers,” IEEE J. Solid-State Circuits, vol. 34, no. 6, pp. 813–821, June 1999.
[30]S.-L. Jang, S.-S. Huang, J.-F. Lee and M.-H. Juang , ” LC-tank Colpitts injection-locked frequency divider with record locking range,” IEEE Microw. Wireless Compon. Lett., pp.560-562, Aug. 2008.
[31]S.-L. Jang, and C.-W. Chang, ” A 90nm CMOS LC-tank divide-by-3 injection-locked frequency divider with record locking range,” IEEE Microw. Wireless Compon. Lett., vol. 20, pp.229-231, April, 2010.
[32]S.-L. Jang, Y.-S. Chen, C.-W. Chang, and C.-C. Liu, ” A wide-locking range ÷3 injection-locked frequency divider using linear mixer,” IEEE Microw. Wireless Compon. Lett., vol. 20, pp.390-392, July, 2010.
[33]S.-L. Jang, Y.-S. Chen, C.-W. Chang and C.-C. Liu,” injection-locked frequency dividing apparatus”, US patent # US008305116B2, 2012.
[34]C.-W. Chang, S.-L. Jang, and C.-W. Hsieh,” Wide-locking range ÷3 active-inductor injection-locked frequency divider using the push-push oscillator,” Microw. Opt. Technol. Lett., pp.2771-2773, Dec, 2011.
[35]Y.-T. Chen, M.-W. Li, H.-C. Kuo, T.-H. Huang, and H.-R. Chuang, “Low-voltage k-Band divide-by-3 injection-locked frequency divider with floating-source differential injector,” IEEE Trans. Microw. Theory Tech., vol. 60, no. 1, pp. 160–67, 2012.
[36]H. Wu and L. Zhang, “A 16-to-18GHz 0.18μm epi-CMOS divide-by-3 injection-locked frequency divider,” in IEEE ISSCC Dig. Tech. Papers, Feb. 2006, pp.27–29.
[37]K. K. Ng and G. W. Taylor, "Effects of hot-carrier trapping in n- and p-channel. MOSFETs," IEEE Trans. Electron Devices,, ED-30, pp. 871, 1983.
[38]K. K. Ng and G. W. Taylor, "Effects of hot-carrier trapping in n- and p-channel. MOSFETs," IEEE Trans. Electron Devices,, ED-30, pp. 871, 1983.
[39]S.-S. Liu, S.-L. Jang, and C.-G. Chyau, " Compact LDD nMOSFET degradation model," IEEE Trans. Electron Devices, Vol. 45, No. 7, pp.1538-1547, 1998.
[40]B. Razavi, RF Microelectronics, NJ: Prentice Hall, Upper Saddle River, 1998.
[41]S.-L. Jang, C.-H. Liu, C.-W. Chang, and M.-H. Juang, " A low voltage, low power divide-by-4 LC-tank injection-locked frequency divider, " Int. J. Electronics., Vol, 98, 4, pp.521-527, April 2011.
[42]H. R. Rategh and T. H. Lee, “Superharmonic injection-locked frequency dividers,” IEEE J. Solid-State Circuits, vol. 34, no. 6, pp. 813–821, June 1999.
[43]Y.-H. Chuang, S.-H. Lee, R.-H. Yen, S.-L. Jang, J.-F. Lee and M.-H. Juang, “A wide locking range and low voltage CMOS direct injection-locked frequency divider,” IEEE Microw. Wireless Compon. Lett., vol. 16, no. 5, pp. 299-301, May 2006.
[44]M. Tiebout, “A CMOS direct injection-locked oscillator topology as high-frequency low-power frequency divider,” IEEE J. Solid-State Circuits, vol. 39, no. 7, pp. 1170 – 1174, July 2004.