本論文提出一個採用電容校正技術之十六位元每秒一百萬次取樣的逐次漸進式類比數位轉換器。對於一個十六位元類比數位轉換器而言，有兩個主要的設計考量。對於雜訊而言，採用靜態前置放大器來抑制比較器所貢獻的雜訊以滿足設計規格。而對於線性度來說本論文採用電容陣列橋接技術降低取樣輸入電容並且達到熱雜訊的規格校正部分為通過 使用數位式電容校正以及電容交換技術來實現。此外，快速二元視窗切換技術被用來輔助電容校正所需要的部份功能，藉由減少不必要的電容切換誤差進一步改善無雜散動態範圍。在台積電的0.18 微米 CMOS 製程下，其晶片面積是 2093平方毫米。在3.3伏特及 1.8伏特 的 操作電壓下，功率消耗為1.427毫瓦。經過電容校正後，在10k赫茲頻率下量測的訊號對雜訊與失真比是 80.32 dB，無雜散動態範圍是93.65 dB，性能指標是 165.7dB。

This thesis is aimed to present a 16-bit successive approximation register analog-to-digital converter (SAR ADC) using capacitor calibration technique. For 16-bit ADCs, there are two main design challenges to conquer. For the noise, the pre-amplifier is proposed to suppress the noise contributed by the comparator to meet specifications. For the linearity, this thesis uses segmented Capacitive Digital-to-Analog Converter (C-DAC) to reduce the sampling capacitor and achieve the specification of the thermal noise. Capacitor calibration and capacitor swapping techniques are proposed to use in the ADC. In addition, the Fast-Binary-Window (FSB) DAC switching scheme is used in this design, and the spurious free dynamic range (SFDR) is improved by eliminating unnecessary capacitor switching errors.
A 16-bit 1MS/s SAR ADC using capacitor calibration technique was implemented in TSMC 180-nm CMOS. The die area of this ADC is2093mm2. It consumes 1.427mW at 3.3 V and 1.8 V supply. After capacitor calibration, at 10kHz, the measured SNDR and SFDR are 80.32 dB and 93.65 dB, respectively. The measured figure of merit (FOM) is 165.7dB.

[1] C. P. Hurrell, et al., "An 18b 12.5MS/s ADC With 93 dB SNR," in IEEE Journal of Solid-State Circuits, vol. 45, no. 12, pp. 2647-2554, Dec. 2010.
[2] A. Bannon, et al., "An 18b 5MS/s SAR ADC with 100.2 dB Dynamic Range," in VLSI Symposium on Circuits, June 2014, pp. 1-2.
[3] M. Maddox, et al., “A 16 bit linear passive-charge-sharing SAR ADC in 55nm CMOS,” in Proc. of IEEE A-SSCC, Nov. 2016, pp. 153-156.
[4] J. Shen, et al., "A 16-bit 16MS/s SAR ADC with On-Chip Calibration in 55nm CMOS," VLSI Symposium on Circuits, Jun, 2017, pp. 282-283.
[5] D. Hummerston, et al., "An 18-bit 2MS/s Pipelined SAR ADC utilizing a sampling distortion cancellation circuit with -107dB THD at 100kHz," VLSI Symposium on Circuits, Jun, 2017, pp. 280-281.
[6] R. Guan, et al., "16-bit 1-MS/s SAR ADC with foreground digital-domain calibration," IET Circuits, Devices & Systems, vol. 12, issue 4, pp. 505-513, 2018.
[7] C. C. Lee, et al., "A 12b 70MS/s SAR ADC with Digital Startup Calibration in 14nm CMOS," VLSI Symposium on Circuits, Jun, 2015, pp. 62-63.
[8] Y.-S. Shu, et al., "An oversampling SAR ADC with DAC mismatch error shaping achieving 105dB SFDR and 101dB SNDR over 1kHz BW in 55nm CMOS," IEEE International Solid-State Circuit Conference, Feb. 2016.
[9] C.-C. Liu, et al., "A 12 bit 100 MS/s SAR-Assisted Digital-Slope ADC," in IEEE Journal of Solid-State Circuits, vol. 51, no. 12, pp. 2941-2950, Dec. 2016.
[10] J. Fredenburg, et al., "A 90MS/s 11MHz Bandwidth 62dB SNDR Noise-Shaping SAR ADC," IEEE International Solid-State Circuit Conference, Feb. 2012. pp. 468-469.
[11] C.-C. Liu, et al., "A 0.46mW 5MHz-BW 79.7dB-SNDR Noise-Shaping SAR ADC with Dynamic-Amplifier-Based FIR-IIR Filter," IEEE International Solid-State Circuit Conference, Feb. 2017. pp. 466-467.
[12] S. Li, et al., "A 13-ENOB 2nd-Order Noise-Shaping SAR ADC Realizing Optimized NTF Zeros Using an Error-Feedback Structure," IEEE International Solid-State Circuit Conference, Feb. 2018. pp. 234-235.
[13] H. Li, et al., “Signal-Independent Background-Calibrating 20b 1MS/s SAR ADC with 0.3ppm INL,” in Proc. of IEEE ISSCC, Feb. 2018, pp. 242-243.
[14] Y.-H. Chung, et al., “A 102dB-SFDR 16bit Calibration-Free SAR ADC in 180-nm CMOS,” IEEE Asia Pacific Conference on Circuits and Systems (APCCAS), Nov. 2019, pp. 5-8.
[15] H.-S. Lee, et al., "A Self-Calibrating 15 Bit CMOS A/D Converter," IEEE J. Solid-State Circuits, vol. SC-19, no. 6, pp. 813–819, Dec. 1984.
[16] W.-H. Tseng, et al., “A 12-bit 104 MS/s SAR ADC in 28 nm CMOS for digitally-assisted wireless transmitters,” in IEEE A-SSCC Dig. Tech. Papers, Nov. 2015, pp. 1–4.
[17] W. Liu, et al., “A 12-bit, 45 MS/s, 3 mW Redundant Successive-Approximation-Register Analog-to-Digital Converter with Digital Calibration,” IEEE J. Solid-State Circuits, vol. 46, no. 11, pp. 2661–2672, Nov. 2011.
[18] R. Xu, et al., "Digitally Calibrated 768-kS/s 10-b Minimum-Size SAR ADC Array With Dithering," IEEE J. Solid-State Circuits, vol. 47, no. 9, pp. 2129–2140, Sep.2012.
[19] A. H. T. Chang, “Low-Power High-Performance SAR ADC With Redundancy and Digital Background Calibration,” Ph.D. dissertation, Dept. Elect. Eng. Comput. Sci., Massachusetts Inst. Technol., Cambridge, MA, USA, 2013.
[20] C.-C Liu, et al., “A 10b 100MS/s 1.13mW SAR ADC with binary scaled error compensation,” in IEEE ISSCC Dig. Tech. Papers, pp.386–387, Feb. 2010.
[21] H.-K Hong, et al., “A Decision-Error-Tolerant 45 nm CMOS 7b 1 GS/s Nonbinary 2b/Cycle SAR ADC,” IEEE Journal of Solid-State Circuits, vol. 50, no. 2, pp. 543-555, Nov, 2015.
[22] M. Dessouky and A. Kaiser, “Input switch configuration suitable for rail-to-rail operation of switched-opamp circuits,” IEE Electron. Letter, vol. 35, pp. 8-10, Jan. 1999.
[23] M. Miyahara, et al., “A low-noise selfcalibrating dynamic comparator for high-speed ADCs,” in Proc. IEEE Asian Solid-State Circuits Conf. (A-SSCC), Nov. 2008, pp. 269–272.
[24] B.-S. Song , et al., “A 1 V 6 b 50 MHz current-interpolating CMOS ADC,” in Symp. VLSI Circuits, 1999, pp. 79-80.
[25] S.-W. M. Chen and R. W. Brodersen, “A 6-bit 600 MS/s 5.3 mW asynchronous ADC in 0.13- μ m CMOS,” IEEE J. Solid-State Circuits, vol. 41, no. 12, pp. 2669–2680, Dec. 2006.
[26] T. Y. Man, et al., Development of single-transistor-control LDO based on flipped voltage follower for SoC,” IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 55, no. 5, pp. 1392–1401, Jun. 2008.