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研究生： 石鈞緯
Chun-Wei Shih
論文名稱： 用於WiMAX應用的5.8 GHz頻段之可調式Gm-C分數型頻率合成器晶片設計
A 5.8 GHz Fractional-N Frequency Synthesizer with Tunable Gm-C Chip Design for WiMAX Application
指導教授： 黃進芳
Jhin-Fang Huang
劉榮宜
Ron-Yi Liu
口試委員: 張勝良
none
徐敬文
none
陳國龍
none
學位類別： 碩士
Master
系所名稱： 電資學院 - 電子工程系
Department of Electronic and Computer Engineering
論文出版年： 2011
畢業學年度： 99
語文別： 英文
論文頁數： 96
中文關鍵詞： 頻率合成器 、分數型
外文關鍵詞： fractional-N
相關次數： 點閱：174  下載：10 
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    • 近年來，以鎖相迴路為主的頻率合成器大量被使用在無線通訊系統中。相對地，各式各樣的頻率合成器就被研發出來。在本篇論文中，設計了一個分數型的頻率合成器，主要是利用了三角積分調變器去實現分數的除數，而三角積分調變器可將量化雜訊移往高頻，再藉由鎖相迴路中迴路頻寬的特色將雜訊濾除，而壓控振盪器的雜訊與充電幫浦和相位頻率檢測器的雜訊的取捨，由迴路頻寬來決定，在晶片實作完成後，為了解決製程變異所造成的誤差，本論文還加入一個可調式的迴路濾波器，並使用考畢子振盪器來降低電路的相位雜訊。

    在本論文中，此頻率合成器使用台積電所提供0.18微米CMOS製程以1.8伏特來完成晶片研製與量測。量測結果顯示頻率鎖定於5.68GHz時，距離主頻1MHz處的相位雜訊為 -112.1 dBc/Hz晶片面積包含pads為1.06 mm2，總消耗功率為56 mW。

    Recently, the PLL-based frequency synthesizers are widely used in wireless communication systems, however, many of PLL architectures are created. In this thesis, we utilized the sigma-delta modulator to perform the fractional-N frequency synthesizer, sigma-delta modulator has high-pass noise shaping ability, and filters high-pass noise through the loop filter of characteristic of phase-locked loop, in addition, the noise of voltage-controlled oscillator and the noise of charge pump and phase frequency detector is a trade-off that is determined by loop bandwidth, in order to solve the problems of variation after implementation of tape out, we added a tunable loop filter, finally the Colpitts voltage-controlled oscillator is adopted to reduce the phase noise.

    In this thesis, the proposed frequency synthesizer is fabricated in a TSMC 0.18-um CMOS process with 1.8 V supply voltage. The measured results show phase noise is -112.1 dBc/Hz at 1 MHz offset from locked in 5.68 GHz. The chip area of the frequency synthesizer is smaller than 1.06 mm2 including the pads. The power consumption is 56 mW from a 1.8-V supply.

    Contents List of Figures III List of Tables VI CHAPTER 1 Introduction 1 1.1 Motivation 1 1.2 Focus and Contributions 2 1.3 Organization of This Thesis 3 CHAPTER 2 The PLL-Based Frequency Synthesizers 4 2.1 Wireless Transceiver 4 2.2 Phase-Locked Loop 5 2.2.1 Integer-N Frequency Synthesizer 6 2.2.2 Fraction-N Frequency Synthesizer 7 2.3 Building Blocks of Frequency Synthesizer 8 2.3.1 Phase Frequency Detector (PFD) 8 2.3.2 Charge Pump (CP) 11 2.3.3 Loop Filter 11 2.3.4 Voltage-Controlled Oscillator (VCO) 12 2.3.5 Frequency Divider 13 2.4 Loop Filter Design 13 2.4.1 First-Order Loop Filter 13 2.4.2 Second-Order Loop 15 2.4.3 Third-Order Loop 17 2.5 Figures of Merit of a Frequency Synthesizer 18 2.5.1 Jitter 18 2.5.2 Phase Noise 19 2.5.3 Spurs 20 2.6 Frequency Synthesizer Paper Survey 21 2.7 Summary 35 CHAPTER 3 Circuits Implementation 36 3.1 Voltage-Controlled Oscillator (VCO) 36 3.1.1 Operation Principle of Oscillator 37 3.1.2 Ring Oscillator 38 3.1.3 LC-Tank Oscillator 39 3.1.4 Passive Components in LC-Tank VCO 42 3.1.5 Switched-Capacitors VCO 48 3.2 Frequency Divider 49 3.2.1 Programmable Frequency Divider 49 3.2.2 Logic Implementation of Frequency Divider 52 3.3 S-D Modulator 53 3.3.1 1st-Order 砥-岛 Modulator 53 3.3.2 Higher-Order 砥-岛 Modulator 56 3.4 Summary 58 CHAPTER 4 5.8 GHz Fractional-N Frequency Synthesizer Chip Design with Tunable Gm-C Loop Filter 59 4.1 Introduction 59 4.2 System Block Diagram 61 4.3 Buliding Block and Simulation 62 4.3.1 Phase Frequency Detector (PFD) 62 4.3.2 Charge Pump (CP) 63 4.3.3 Voltage-Controlled Oscillator 65 4.3.4 Frequency Divider 68 4.3.5 MASH 1-1-1 砥-岛汹Modulator 71 4.3.6 Gm-C Loop Filter 73 4.4 Overall System Simulation Results and Specification 77 4.5 Summary 80 CHAPTER 5 Chip Measurement Results 81 5.1 RF Chip Layout Considerations 81 5.2 RF Chip Measurement Considerations 82 5.2.1 Chip Floor Plan and PCB Design 82 5.2.2 Test Environment Setup 84 5.3 Measurement Results 85 5.4 Performance Summary and Comparison 87 CHAPTER 6 Conclusions and Future Work 89 6.1 Conclusions 89 6.2 Future Work 89 Reference 91

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