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研究生： 楊奇峻
Chi-jiun Yang
論文名稱： 發光及接收元件與鎖相迴路積體電路於通訊之應用
Light Emitting and Receiving Devices and Phase-Locked-Loop Integrated Circuits for Communications
指導教授： 劉政光
Cheng-kuang Liu
口試委員: 張嘉男
Chia-nan Chang
周肇基
Chao-chi Chou
徐世祥
Shih-hsiang Hsu
學位類別： 碩士
Master
系所名稱： 電資學院 - 電子工程系
Department of Electronic and Computer Engineering
論文出版年： 2008
畢業學年度： 96
語文別： 英文
論文頁數： 121
中文關鍵詞： 頻率合成器 、時脈資料回復電路 、鎖相迴路 、光偵測器
外文關鍵詞： frequency synthesizer, CDR, PLL, photo detector
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    • 本論文研究發光與接收元件，以及應用於通訊中使用鎖相迴路技術在積體電路晶片之實作，包含應用於光通訊中的光接收與發光元件、時脈資料回復電路、應用於無線通訊中的頻率合成器。
    第一種晶片是以TSMC 0.35μm 3P3M SiGe BiCMOS 3.3V製程實現，應用於光通訊傳輸與接收器上的矽鍺基發光與接收偵測元件。
    第二種晶片是應用於光接收器之鎖相迴路式時脈資料回復電路，是以TSMC 0.18μm 1P6M CMOS製程來實現1.25Gb/s的光通訊積體電路。時脈資料回復電路中討論與設計包含了相位偵測器、電荷幫浦、迴路濾波器和壓控震盪器。本晶片面積為0.697591 x 0.957154 mm2 ，在1.8伏特的電壓下功率消耗為36mW。
    第三種晶片是應用於無線通訊之鎖相迴路式頻率合成器，是以TSMC 0.18μm 1P6M CMOS製程來實現，面積佔1.072408 x 1.189363 mm2 ，可產生2GHz的穩定時脈，在偏移中心載波頻率1MHz處所量測到的相位雜訊為-106.31dBc/Hz，可調頻率範圍從1.795GHz到2.07GHz，在1.8伏特的電壓下消耗功率為50mW。

    This thesis presents chips for communications; it includes the light emitting and receiving devices and the phase-locked-loop related integrated circuits, such as the clock and data recovery for optical communication, the frequency synthesizer for wireless communication.
    The first chip is a SiGe-Based light emitting and photo detection device. It is for the light emitting and receiving in the transmitter and receiver for optical communication and is fabricated in the TSMC 0.35μm 3P3M SiGe BiCMOS 3.3V technology.
    The second chip is a PLL-based clock and data recovery circuit (CDR) for application to optical receiver. Fabricated by TSMC 0.18μm 1P6M CMOS 1.8V technology, the CDR circuit is for 1.25Gb/s optical communication. The building blocks of CDR that including phase detector, charge pump, loop filter and VCO are discussed. The power consumption of the CDR is 36 mW under 1.8V supply voltages. The area is 0.697591 x 0.957154 mm2 .
    The third chip is a PLL-based frequency synthesizer for wireless communication. It is fabricated in the TSMC 0.18μm 1P6M CMOS 1.8V technology and has an area of 1.072408 x 1.189363 mm2 . A 2GHz steady clock is achieved. The measured phase noise is –106.31dBc/Hz at 1 MHz offset from the carrier. Tuning range is from 1.795GHz to 2.07GHz. It consumes a power of 50 mW from a 1.8-V supply voltage.

    論文摘要..........................................I Abstract.........................................II 誌謝.............................................IV Contents..........................................V List of Figures................................VIII List of Tables.................................XIII CHAPTER 1 Introduction...................................1 1.1 Motivation...........................................1 1.2 Optical Communication Transceiver....................2 1.3 Thesis Organization..................................3 CHAPTER 2 Design of SiGe-Based Light Emitting and Photo Dectection Devices.......................................4 2.1 The Concepts of SiGe-Based Light Emitting and Photo Detection Devices........................................4 2.2 Circuit Implementation...............................7 2.2.1 Principle Operation of Photodiode..................7 2.2.2 Equivalent Circuit of SiGe Photodiode..............9 2.2.3 Current vs. Voltage Characteristics...............11 2.2.4 SiGe-based Photodetectors.........................13 2.2.5 Device structures.................................14 2.3 Experimental Results................................17 2.3.1 Implement SiGe-Based Light Emitting Devices.......18 2.3.1.1 Forward Bias Measurement........................18 2.3.1.2 Reverse Bias Measurement........................21 2.3.2 Results of SiGe-Based Receiving Devices...........22 2.4 Discussion..........................................31 CHAPTER 3 Design of Clock and Data Recovery Circuit.....33 3.1 The Concepts of Clock and Data Recovery Circuit.....33 3.1.1 Data Formats......................................34 3.1.2 Generation of Random Binary Data..................35 3.1.3 Simple Clock and Data Recovery Circuit............37 3.1.4 Eye Diagram.......................................39 3.1.5 Eye Diagram Program...............................40 3.1.6 Jitter Separation.................................43 3.2 Circuit Implementation..............................44 3.2.1 Full-Rate and Half-Rate CDR Architectures.........44 3.2.2 CDR Architecture..................................46 3.2.3 Phase Detector....................................48 3.2.3.1 Hogge Phase Detector............................48 3.2.3.2 Alexander Phase Detector........................52 3.2.4 Charge Pump.......................................56 3.2.4.1 Charge Pump Architecture........................57 3.2.5 Loop Filter.......................................58 3.2.6 CML(Current-Mode Logic)...........................60 3.2.7 Cherry-Hooper Amplifier & XOR.....................61 3.2.8 Voltage-Controlled Oscillator (VCO)...............62 3.2.8.1 Cross-Coupled Oscillator........................62 3.2.8.2 Complementary Cross-Coupled Oscillator..........63 3.2.8.3 VCO Architecture................................65 3.3 Experimental results................................67 3.3.1 CDR System Simulation Results.....................67 3.3.2 CDR Measurement Results...........................77 3.4 Discussion..........................................79 CHAPTER 4 Design of Frequency Synthesizer...............80 4.1 The Concepts of Frequency Synthesizer...............80 4.1.1 General Concepts..................................81 4.2 Circuit Implementation..............................85 4.2.1 Frequency Synthesizer Architecture................85 4.2.2 Phase Frequency Detector..........................87 4.2.3 VCO Architecture..................................91 4.2.4 Preamplifier ......................................92 4.2.5 Programmable Frequency Divider....................93 4.2.5.1 The dual-modulus prescaler......................94 4.2.5.2 Programmable Counter............................96 4.2.5.3 Swallow Counter.................................99 4.3 Experimental Results...............................100 4.3.1 Frequency Synthesizer Simulation Results.........100 4.3.2 Frequency Synthesizer Measurement Results........110 4.4 Discussion.........................................114 CHAPTER 5 Conclusions and Future Perspectives..........115 5.1 Conclusions........................................115 5.2 Future perspectives................................116 References.............................................117 VITA...................................................121

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