簡易檢索 / 詳目顯示

研究生: 李修竹
Xiu-Zhu Li
論文名稱: 嵌入式類比快閃記憶體之低功耗智能感測電路與系統
Low Power Intelligence Sensing Circuits and Systems Using Embedded Analog Flash Memories
指導教授: 彭盛裕
Sheng-Yu Peng
口試委員: 彭盛裕
Sheng-Yu Peng
洪浩喬
Hao-Chiao Hong
鄭桂忠
Kea-Tiong Tang
學位類別: 碩士
Master
系所名稱: 電資學院 - 電機工程系
Department of Electrical Engineering
論文出版年: 2024
畢業學年度: 112
語文別: 英文
論文頁數: 144
中文關鍵詞: 瞬時增強電流自適應放大器認知運算記憶內的計算 低功耗電路
外文關鍵詞: transient enhancement, current adaptive amplifier, cognitive computation, computing in memories, low-power circuits
相關次數: 點閱:518下載:0
分享至:
查詢本校圖書館目錄 查詢臺灣博碩士論文知識加值系統 勘誤回報

  • Abstract in Chinese i Abstract in English ii Acknowledgements iv Contents vi List of Figures x List of Tables xix 1 Introduction 1 1.1 Motivation 1 1.2 Thesis Organization 3 2 Background Knowledge 5 2.1 Biomedical Signal Characteristics 5 2.2 Floating Gate Transistors 7 2.3 Recurrent Neuron Network 11 3 A Transient­Enhanced Autonomous Current Adaptation Buffer Amplifier 15 3.1 Literature Review 15 3.2 Review of Prior Work 16 3.3 Circuit implementation 21 3.4 Measurement Results 24 3.5 Conclusion and Comparison 27 4 Autonomous Current Adaptation ADC Input Driver 29 4.1 Literature Review 30 4.1.1 ∆Vmax Diminution 31 4.1.2 TS Extension 33 4.1.3 CL Reduction 34 4.2 Circuit Implementation 35 4.3 Measurement Results 39 4.4 Conclusion and Comparison 41 5 SRAM­Based Reconfigurable Cognitive Computation Matrix 45 5.1 Literature Review 46 5.2 Data Representation 49 5.3 Circuit Implementation 54 5.3.1 Architecture 54 5.3.2 Processing Elements and Input Auxiliary Control Block 55 5.3.3 Activation Function Circuits 59 5.4 Measurement Results 60 5.4.1 Multiplication and Operation 61 5.4.2 Activation Function Characterization 63 5.4.3 Process Variation and Calibration 65 5.4.4 Demonstration 68 5.5 Conclusion and Comparison 72 6 Analog Flash­Based Analog Gated Recurrent Unit 76 6.1 Literature Review 77 6.2 Hardware­Friendly Software Model 78 6.3 Circuit implementation 81 6.3.1 Architecture 82 6.3.2 Vector Matrix Multiplication 83 6.3.3 Input Class­AB OTA 87 6.3.4 Single­to­Differential Converter 90 6.3.5 Activation Function Circuit 91 6.3.6 Current­Mode Low­Pass Filter 93 6.3.7 Winner­Take­All Circuit 95 6.4 Software­Hardware Co­Design 97 6.4.1 Input Signal Pre­Process 98 6.4.2 Activation Function Mapping 102 6.4.3 Time Constant Mapping 104 6.4.4 Spike Sorting Simulation 105 6.5 Measurement Results 110 6.5.1 Vector Matrix Multiplication 111 6.5.2 Calibration 113 6.5.3 Single­to­Differential Converter 114 6.5.4 Activation Function Circuit 116 6.5.5 Current­Mode Low­Pass Filter 118 6.5.6 Winner­Take­All Circuit 119 6.6 Conclusion and Comparison 120 7 Conclusion 123 8 Contribution 126 References 128

    [1] Z.­J. Lo et al., “A reconfigurable differential­to­single­ended autonomous cur­ rent adaptation buffer amplifier suitable for biomedical applications,” IEEE Trans. Biomed. Circuits Syst., vol. 15, pp. 1405–1418, Dec 2021.
    [2] 黃筠傑, ” 利用嵌入式類比快閃記憶體技術設計之暫態增強自適功率調變緩衝放大器積體電路設計”. 國立臺灣科技大學碩士論文, 2023.
    [3] 蕭宗益, ” 類比記憶體編成之積體電路設計與系統整合”. 國立臺灣科技大學碩士論文, 2015.
    [4] 黃惠群, ” 適用於生醫應用之低功耗可編程四通道類比感測前端電路與使用線性提升技術之轉導電容濾波器”. 國立臺灣科技大學碩士論文, 2019.
    [5] Z.­J. Lo et al., “A transient­enhanced autonomous current adaptation buffer ampli­ fier,” IEEE Trans. Circuits Syst. II: Exp. Briefs, vol. 70, pp. 3727–3731, Oct 2023.
    [6] Z.­J. Lo et al., “A power­efficient autonomous current adaptation adc input driver,”IEEE Trans. Circuits Syst. I: Reg. Papers, 2024.
    [7] V. Sharma, J. E. Kim, Y.­J. Jo, Y. Chen, and T. T.­H. Kim, “And8t sram macro with improved linearity for multi­bit in­memory computing,” in 2021 IEEE Inter­ national Symposium on Circuits and Systems (ISCAS), pp. 1–5, 2021.
    [8] S. Yin, Z. Jiang, J.­S. Seo, and M. Seok, “Xnor­sram: In­memory computing sram macro for binary/ternary deep neural networks,” IEEE Journal of Solid­State Cir­ cuits, vol. 55, no. 6, pp. 1733–1743, 2020.
    [9] Q. Dong et al., “15.3 a 351tops/w and 372.4gops compute­in­memory sram macro in 7nm finfet cmos for machine­learning applications,” 2020 IEEE International Solid­State Circuits Conference ­ (ISSCC), pp. 242–244, 2020.
    [10] A. Biswas and A. P. Chandrakasan, “Conv­sram: An energy­efficient sram with in­ memory dot­product computation for low­power convolutional neural networks,” IEEE Journal of Solid­State Circuits, vol. 54, no. 1, pp. 217–230, 2019.
    [11] S.­Y. Peng et al., “An sram­based reconfigurable cognitive computation matrix for sensor edge applications,” IEEE J. Solid­State Circuits, vol. 59, pp. 636–648, Feb 2024.
    [12] F. Kusumoto, ECG Interpretation: From Pathophysiology to Clinical Application.Berlin, Germany: Springer, 2020.
    [13] D. Kahng and S. M. Sze, “A floating­gate and its application to memory devices,”Bell System Tech. J., vol. 46, no. 4, pp. 1288–1295, 1967.
    [14] M. Holler et al., “An electrically trainable artificial neural network with 10240 floating gate synapses,” in Proceedings of the International Joint Conference on Neural Networks, (Washington, D.C.), 1989.
    [15] A. Thomsen and M. A. Brooke, “A floating gate mosfet with tunneling injector fab­ ricated using a standard double­polysilicon cmos process,” IEEE Electron Device Lett., vol. 12, pp. 111–113, 1991.
    [16] C. Mead et al., Analog VLSI Implementation of Neural Systems. Kluwer Academic Publishers, 1989.
    [17] T. Shibata and T. Ohmi, “A functional mos transistor featuring gate­level weighted sum and threshold operations,” IEEE Trans. Electron Devices, vol. 39, no. 6, pp. 1444–1455, 1992.
    [18] P. Hasler, Foundations of Learning in Analog VLSI. PhD thesis, California Institute of Technology, 1997.
    [19] V. Srinivasan et al., “A precision cmos amplifier using floating­gate transistors for offset cancellation,” IEEE J. Solid­State Circuits, vol. 42, pp. 280–291, Feb 2007.
    [20] G. Serrano and P. Hasler, “A precision low­tc wide­range cmos current reference,”IEEE J. Solid­State Circuits, vol. 43, pp. 558–565, Feb 2008.
    [21] D. W. Graham et al., “A low­power programmable bandpass filter section for higher order filter applications,” IEEE Trans. Circuits Syst. I, vol. 54, Jun 2007.
    [22] T. S. Hall et al., “Application performance of elements in a floating­gate fpaa,” in Proceedings of IEEE International Symposium on Circuits and Systems, pp. 589– 592, Oct 2004.
    [23] A. Basu et al., “A floating­gate­based field­programmable analog array,” IEEE J. Solid­State Circuits, vol. 45, pp. 1781–1794, Sept 2010.
    [24] S. George et al., “A programmable and configurable mixed­mode fpaa soc,” IEEE Trans. VLSI Syst., vol. 24, pp. 2253–2261, Jun 2016.
    [25] S. Shah and J. Hasler, “Soc fpaa hardware implementation of a vmm+wta embedded learning classifier,” IEEE J. Emerg. Sel. Top. Circuits Syst., vol. 8, Mar 2018.
    [26] A. Natarajan and J. Hasler, “Hodgkin–huxley neuron and fpaa dynamics,” IEEE Trans. Biomed. Circuits Syst., vol. 12, pp. 918–926, Jul 2018.
    [27] R. Guo, Y. Liu, S. Zheng, S. Wu, P. Ouyang, W. Khwa, X. Chen, J. Chen, X. Li, L. Liu, M. Chang, S. Wei, and S. Yin, “A 5.1 pj/neuron 127.3 us/inference rnn­ based speech recognition processor using 16 computing­in­memory sram macros in 65 nm cmos,” in 2019 Symposium on VLSI Circuits, pp. C120–C121, 2019.
    [28] D. Kadetotad, S. Yin, V. Berisha, C. Chakrabarti, and J. Seo, “An 8.93 tops/w lstm recurrent neural network accelerator featuring hierarchical coarse­grain sparsity for on­device speech recognition,” IEEE Journal of Solid­State Circuits, vol. 55, no. 7, pp. 1877–1887, 2020.
    [29] K. Kim, C. Gao, R. Graça, I. Kiselev, H. Yoo, T. Delbruck, and S. Liu, “A 23μw solar­powered keyword­spotting asic with ring­oscillator­based time­domain feature extraction,” in 2022 IEEE International Solid­State Circuits Conference (ISSCC), vol. 65, pp. 1–3, 2022.
    [30] C. Frenkel and G. Indiveri, “Reckon: A 28nm sub­mm2 task­agnostic spiking recurrent neural network processor enabling on­chip learning over second­long timescales,” in 2022 IEEE International Solid­State Circuits Conference (ISSCC), vol. 65, pp. 1–3, 2022.
    [31] K.­J. de Langen and J. H. Huijsing, “Compact low­voltage power­efficient opera­ tional amplifier cells for vlsi,” IEEE J. Solid­State Circuits, vol. 33, pp. 1482–1496, Oct 1998.
    [32] J. R.­Angulo, R. G. Carvajal, J. A. Galan, and A. J. L.­Martin, “A free but efficient low­voltage class­ab two­stage operational amplifier,” IEEE Trans. Circuits Syst. II: Exp. Briefs, vol. 53, pp. 568–571, Jul 2006.
    [33] P. R. Surkanti and P. M. Furth, “Converting a three­stage pseudoclass­ab amplifier to a true­class­ab amplifier,” IEEE Trans. Circuits Syst. II: Exp. Briefs, vol. 59, pp. 229–233, Apr 2012.
    [34] C. G.­Alberdi, J. A.­Ruiz, A. J. L.­Martin, and J. R.­Angulo, “Micropower class­ab vga with gain­independent bandwidth,” IEEE Trans. Circuits Syst. II: Exp. Briefs, vol. 60, pp. 397–401, Jul 2013.
    [35] F. E.­Alfaro, S. Pennisi, G. Palumbo, and A. J. L.­Martin, “Low­power class­ab cmos voltage feedback current operational amplifier with tunable gain and band­ width,” IEEE Trans. Circuits Syst. II: Exp. Briefs, vol. 61, pp. 574–578, Aug 2014.
    [36] E. C.­Bernal, S. Pennisi, A. D. Grasso, A. Torralba, and R. G. Carvajal, “0.7­v three­ stage class­ab cmos operational transconductance amplifier,” IEEE Trans. Circuits Syst. I: Fundam. Theory Appl., vol. 63, pp. 1807–1815, Nov 2016.
    [37] M. Degrauwe, J. Rijmenants, E. A. Vittoz, and D. Man, “Adaptive biasing cmos amplifier,” IEEE Journal of Solid­State Circuits, vol. SC­17, pp. 522–528, Jun. 1982.
    [38] R. Kline, B. J. Hosticka, and H. J. Pfleiderer, “A very­high­slew­rate cmos opera­ tional amplifier,” IEEE Journal of Solid­State Circuits, vol. 24, pp. 744–760, Jun. 1989.
    [39] L. Callewaert and W. Sansen, “Class­ab cmos amplifiers with high efficiency,”IEEE Journal of Solid­State Circuits, vol. 25, pp. 684–691, Jun. 1990.
    [40] A. J. López­Martín, S. Baswa, J. R. Rincón­Mora, and R. G. Carvajal, “Low­ voltage super class­ab cmos ota cells with very high slew rate and power effi­ ciency,” IEEE Journal of Solid­State Circuits, vol. 40, pp. 1068–1077, May 2005.
    [41] B. A. Minch, “A simple class­ab transconductor in cmos,” in Proc. IEEE Int. Symp. Circuits Syst., pp. 69–72, 2008.
    [42] D. Du and K. M. Odame, “A bandwidth­adaptive preamplifier,” IEEE Journal of Solid­State Circuits, vol. 48, pp. 2142–2153, Sep. 2013.
    [43] R. Castello and P. R. Gray, “A high­performance micropower switched­capacitor filter,” IEEE Journal of Solid­State Circuits, vol. SC­20, pp. 1122–1132, Dec. 1985.
    [44] R. Harjani, R. Heineke, and F. Wang, “An integrated low­voltage class­ab cmos ota,” IEEE Journal of Solid­State Circuits, vol. SC­34, pp. 134–142, Feb. 1999.
    [45] A. J. López­Martín, M. P. Garde, J. M. Algueta, C. A. C. Blas, R. G. Carvajal, and J. Rincón­Mora, “Enhanced single­stage folded cascode ota suitable for large capacitive loads,” IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 65, pp. 441–445, Apr. 2018.
    [46] M. P. Garde, A. J. López­Martín, R. G. Carvajal, and J. Rincón­Mora, “Super class­ ab recycling folded cascode ota,” IEEE Journal of Solid­State Circuits, vol. 53, pp. 2614–2623, Sep. 2018.
    [47] M. Garde, A. Lopez­Martin, R.G.Carvajal, and J.Ramirez­Angulo, “Super class­ AB recycling folded cascode OTA,” IEEE Journal of Solid­State Circuits, vol. 53, no. 22, pp. 2614–2623, 2018.
    [48] A. Paul, J. R.­Angulo, A. D. Sanchez, A. J. L.­Martin, R. G. Carvajal, and F. X. Li, “Super­gain­boosted AB­AB fully differential miller Op­Amp with 156dB open­ loop gain and 174MV/V MHz pF/µW figure of merit in 130nm CMOS technology,” vol. 9, pp. 57603–57617, 2021.
    [49] J. B.­Legarra, C. A. C.­Blas, A. J. L.­Martin, and J. R.­Angulo, “Gain­boosted super class AB OTA based on nested local feedback,” IEEE Transactions on Circuits and Systems I: Fundamental Theory and Applications, vol. 68, no. 9, pp. 3562–3573, 2021.
    [50] H. S. Bindra, J. Lechevallier, A. J. Annema, S. M. Louwsma, E. V. Tuijl, and B. Nauta, “Range pre­selection sampling technique to reduce input drive energy for sar adcs,” in IEEE Proceedings of the Asian Solid­State Circuits Conference (A­SSCC), pp. 217–220, 2017.
    [51] L. Wei, X. H. Pan, C. H. Chan, Y. Zhu, and R. P. Martins, “Input correlated swap­ sampling technique for input driver power reduction in a 12b 25ms/s sar adc,” in IEEE Proceedings of the International Symposium on Circuits and Systems, pp. 1– 5, 2019.
    [52] H. S. Bindra, A. J. Annema, S. M. Louwsma, E. V. Tuijl, and B. Nauta, “An energy reduced sampling technique applied to a 10bits 1ms/s sar adcs,” in IEEE European Solid­State Circuits Conference, pp. 238–238, 2017.
    [53] X. Zou et al., “A 100­channel 1­mw implantable neural recording ic,” IEEE Trans­ actions on Circuits and Systems I: Regular Papers, vol. 60, pp. 2584–2596, Oct 2013.
    [54] M. J. Kramer, E. Janssen, K. Doris, and B. Murmann, “A 14 b 35ms/s sar adc achieving 75 db sndr and 99 db sfdr with loop­embedded input buffer in 40 nm cmos,” IEEE Journal of Solid­State Circuits, vol. 50, no. 12, pp. 2891–2900, 2015.
    [55] T. Kim and Y. Chae, “A 2mhz bw buffer­embedded noise­shaping sar adc achiev­ ing 73.8db sndr and 87.3db sfdr,” in IEEE Proceedings of the Custom Integrated Circuits Conference, pp. 1–4, 2019.
    [56] J. Liu, X. Tang, W. Zhao, L. Shen, and N. Sun, “A 13­bit 0.005­mm² 40­ms/s sar adc with kt/c noise cancellation,” IEEE Journal of Solid­State Circuits, vol. 55, no. 12, pp. 3260–3270, 2020.
    [57] S. Li, “A kt/c­noise­cancelled noise­shaping sar adc with a duty­cycled amplifier,” in IEEE Proceedings of the International Midwest Symposium on Circuits and Sys­ tems, pp. 758–761, 2020.
    [58] T.­H. Wang, R. Wu, V. Gupta, X. Tang, and S. Li, “A 13.8­enob fully dynamic third­ order noise­shaping sar adc in a single­amplifier ef­ciff structure with hardware­ reusing kt/ c noise cancellation,” IEEE Journal of Solid­State Circuits, vol. 56, no. 12, pp. 3268–3680, 2021.
    [59] M. Zhan, L. Jie, X. Tang, and N. Sun, “A 0.004mm² 200ms/s pipelined sar adc with kt/c noise cancellation and robust ring­amp,” in IEEE Proceedings of the Interna­ tional Solid­State Circuits Conference (ISSCC), vol. 65, pp. 164–166, 2022.
    [60] Z.­J. Lo, B. Nath, Y.­C. Wang, Y.­J. Haung, H.­C. Haung, and S.­Y. Peng, “A floating­gate­based four­channel reconfigurable analog front­end integrated cir­ cuit,” in Proc. IEEE Int. Symp. Circuits Syst., pp. 1–4, May 2021.
    [61] H. S. Bindra, J. Lechevallier, A. J. Annema, S. M. Louwsma, E. V. Tuijl, and B. Nauta, “Range pre­selection sampling technique to reduce input drive energy for sar adcs,” IEEE Proceedings of the Asian Solid­State Circuits Conference (A­ SSCC), pp. 217–220, 2017.
    [62] H. S. Bindra, A. J. Annema, S. M. Louwsma, E. V. Tuijl, and B. Nauta, “An energy reduced sampling technique applied to a 10bits 1ms/s sar adcs,” pp. 238–238, 2017.
    [63] X. Zou, L. Liu, J. H. Cheong, L.Yao, P. Li, M. Y. Cheng, W. L. Goh, R. Rajkumar, G. S. Dawe, K. W. Cheng, and M. Je, “A 100­channel 1­mw implantable neural recording ic,” IEEE Transactions on Circuits and Systems I: Fundamental Theory and Applications, vol. 60, no. 10, pp. 2584–2596, 2013.
    [64] T. Kim and Y. Chae, “A 2mhz bw buffer­embedded noise­shaping sar adc achieving 73.8db sndr and 87.3db sfdr,” IEEE Proceedings of the Custom Integrated Circuits Conference, pp. 1–4, 2019.
    [65] Y. M. Chae, W. Liu, Z. Yang, T. Chen, J. Kim, M. Sivaprakasam, and M. Yuce, “A 128­channel 6 mw wireless neural recording ic with on­the­ fly spike sorting and uwb transmitter,” pp. 146–147, 2008.
    [66] K. M. A.­Ashmouny, S. I. Chang, and E. Yoon, “A 4µw/ch analog front­end mod­ ule with moderate inversion and power­scalable sampling operation for 3­d neural microsystems,” IEEE Transactions on Biomedical Circuits and Systems, vol. 6, no. 5, pp. 403–413, 2012.
    [67] C. M. Lopez, D. Prodanov, D. Braeken, I. Gligorijevic, E. Eberle, C. Bartic, R. Puers, and G. Gielen, “A multichannel integrated circuit for electrical recording of neural activity, with independent channel programmability,” IEEE Transactions on Biomedical Circuits and Systems, vol. 6, no. 2, pp. 101–110, 2012.
    [68] C.­Y. Wu, C.­H. Cheng, and Z.­X. Chen, “16­channel cmos chopper­stabilized ana­ log front­end ecog acquisition circuit for a closed­loop epileptic seizure control system,” IEEE Transactions on Biomedical Circuits and Systems, vol. 12, no. 3, pp. 543–553, 2018.
    [69] J. Zhang, Z. Wang, and N. Verma, “In­memory computation of a machine­learning classifier in a standard 6t sram array,” IEEE Journal of Solid­State Circuits, vol. 52, no. 4, pp. 915–924, 2017.
    [70] W.­S. Khwa, J.­J. Chen, J.­F. Li, X. Si, E.­Y. Yang, X. Sun, R. Liu, P.­Y. Chen, Q. Li, S. Yu, and M.­F. Chang, “A 65nm 4kb algorithm­dependent computing­in­memory sram unit­macro with 2.3ns and 55.8tops/w fully parallel product­sum operation for binary dnn edge processors,” in 2018 IEEE International Solid­State Circuits Conference ­ (ISSCC), pp. 496–498, 2018.
    [71] R. Liu, X. Peng, X. Sun, W.­S. Khwa, X. Si, J.­J. Chen, J.­F. Li, M.­F. Chang, and S. Yu, “Parallelizing sram arrays with customized bitcell for binary neural net­ works,” in 2018 55th ACM/ESDA/IEEE Design Automation Conference (DAC), pp. 1–6, 2018.
    [72] H. Valavi, P. J. Ramadge, E. Nestler, and N. Verma, “A mixed­signal bina­ rized convolutional­neural­network accelerator integrating dense weight storage and multiplication for reduced data movement,” in 2018 IEEE Symposium on VLSI Circuits, pp. 141–142, 2018.
    [73] A. Agrawal, A. Jaiswal, D. Roy, B. Han, G. Srinivasan, A. Ankit, and K. Roy, “Xcel­ram: Accelerating binary neural networks in high­throughput sram compute arrays,” IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 66, no. 8, pp. 3064–3076, 2019.
    [74] H. Valavi, P. J. Ramadge, E. Nestler, and N. Verma, “A 64­tile 2.4­mb in­memory­ computing cnn accelerator employing charge­domain compute,” IEEE Journal of Solid­State Circuits, vol. 54, no. 6, pp. 1789–1799, 2019.
    [75] J. Yang, Y. Kong, Z. Wang, Y. Liu, B. Wang, S. Yin, and L. Shi, “24.4 sandwich­ ram: An energy­efficient in­memory bwn architecture with pulse­width modu­ lation,” in 2019 IEEE International Solid­State Circuits Conference ­ (ISSCC), pp. 394–396, 2019.
    [76] Z. Jiang, S. Yin, J.­S. Seo, and M. Seok, “C3sram: An in­memory­computing sram macro based on robust capacitive coupling computing mechanism,” IEEE Journal of Solid­State Circuits, vol. 55, no. 7, pp. 1888–1897, 2020.
    [77] J. Mu, H. Kim, and B. Kim, “Sram­based in­memory computing macro featuring voltage­mode accumulator and row­by­row adc for processing neural networks,” IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 69, no. 6, pp. 2412–2422, 2022.
    [78] C. Yu, T. Yoo, K. T. C. Chai, T. T.­H. Kim, and B. Kim, “A 65­nm 8t sram compute­ in­memory macro with column adcs for processing neural networks,” IEEE Journal of Solid­State Circuits, pp. 1–1, 2022.
    [79] X. Si, J.­J. Chen, Y.­N. Tu, W.­H. Huang, J.­H. Wang, Y.­C. Chiu, W.­C. Wei, S.­Y. Wu, X. Sun, R. Liu, S. Yu, R.­S. Liu, C.­C. Hsieh, K.­T. Tang, Q. Li, and M.­F. Chang, “A twin­8t SRAM computation­in­memory unit­macro for multibit CNN­ based AI edge processors,” IEEE Journal of Solid­State Circuits, vol. 55, no. 1, pp. 189–202, 2020.
    [80] X. Si, Y.­N. Tu, W.­H. Huang, J.­W. Su, P.­J. Lu, J.­H. Wang, T.­W. Liu, S.­Y. Wu,R. Liu, Y.­C. Chou, Y.­L. Chung, W. Shih, C.­C. Lo, R.­S. Liu, C.­C. Hsieh, K.­T. Tang, N.­C. Lien, W.­C. Shih, Y. He, Q. Li, and M.­F. Chang, “A local computing cell and 6t SRAM­based computing­in­memory macro with 8­b MAC operation for edge AI chips,” IEEE Journal of Solid­State Circuits, vol. 56, no. 9, pp. 2817–2831, 2021.
    [81] M. E. Sinangil, B. Erbagci, R. Naous, K. Akarvardar, D. Sun, W.­S. Khwa, H.­J. Liao, Y. Wang, and J. Chang, “A 7­nm compute­in­memory SRAM macro sup­ porting multi­bit input, weight and output and achieving 351 TOPS/W and 372.4 GOPS,” IEEE Journal of Solid­State Circuits, vol. 56, no. 1, pp. 188–198, 2021.
    [82] H. Fujiwara, H. Mori, W.­C. Zhao, M.­C. Chuang, R. Naous, C.­K. Chuang, T. Hashizume, D. Sun, C.­F. Lee, K. Akarvardar, S. Adham, T.­L. Chou, M. E. Sinangil, Y. Wang, Y.­D. Chih, Y.­H. Chen, H.­J. Liao, and T.­Y. J. Chang, “A 5­ nm 254­tops/w 221­tops/mm² fully­digital computing­in­memory macro support­ ing wide­range dynamic­voltage­frequency scaling and simultaneous mac and write operations,” in 2022 IEEE International Solid­State Circuits Conference (ISSCC), vol. 65, pp. 1–3, 2022.
    [83] P.-C. Wu, J.-W. Su, Y.-L. Chung, L.-Y. Hong, J.-S. Ren, F.-C. Chang, Y. Wu, H.-Y. Chen, C.-H. Lin, H.-M. Hsiao, S.-H. Li, S.-S. Sheu, S.-C. Chang, W.-C. Lo, C.-C. Lo, R.-S. Liu, C.-C. Hsieh, K.-T. Tang, C.-I. Wu, and M.-F. Chang, “A 28nm 1mb time-domain computing-in-memory 6t-sram macro with a 6.6ns latency, 1241gops and 37.01tops/w for 8b-mac operations for edge-ai devices,” in 2022 IEEE Inter­ national Solid­State Circuits Conference (ISSCC), vol. 65, pp. 1–3, 2022.
    [84] B. Yan, J.-L. Hsu, P.-C. Yu, C.-C. Lee, Y. Zhang, W. Yue, G. Mei, Y. Yang, Y. Yang, H. Li, Y. Chen, and R. Huang, “A 1.041-mb/mm² 27.38-tops/w signed- int8 dynamic-logic-based adc-less sram compute-in-memory macro in 28nm with reconfigurable bitwise operation for ai and embedded applications,” in 2022 IEEE International Solid­State Circuits Conference (ISSCC), vol. 65, pp. 188–190, 2022.
    [85] H. Fujiwara, H. Mori, W.-C. Zhao, M.-C. Chuang, R. Naous, C.-K. Chuang, T. Hashizume, D. Sun, C.-F. Lee, K. Akarvardar, S. Adham, T.-L. Chou, M. E. Sinangil, Y. Wang, Y.-D. Chih, Y.-H. Chen, H.-J. Liao, and T.-Y. J. Chang, “A 5- nm 254-TOPS/W 221-TOPS/mm² fully-digital computing-in-memory macro sup- porting wide-range dynamic-voltage-frequency scaling and simultaneous MAC and write operations,” in 2022 IEEE International Solid­State Circuits Conference (ISSCC), vol. 65, pp. 1–3, 2022.
    [86] J. Ramirez-Angulo, R. Carvajal, and A. Torralba, “Low supply voltage high performance CMOS current mirror with low input and output voltage requirements,” IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 51, no. 3, pp. 124–129, 2004.
    [87] T. Delbruck, ““bump” circuits for computing similarity and dissimilarity of analog voltages,” in Proc. Int. Neural Netw. Soc., vol. 1, pp. 475–479, Oct 1991.
    [88] X. Qiao, J. Song, X. Tang, H. Luo, N. Pan, X. Cui, R. Wang, and Y. Wang, “A 65 nm 73 kb sram-based computing-in-memory macro with dynamic-sparsity controlling,” IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 69, no. 6, pp. 2977–2981, 2022.
    [89] A. Canhoto and S. Arp, “Exploring the factors that support adoption and sustained use of health and fitness wearables,” J. Marketing Manage., vol. 33, pp. 32–60, 2017.
    [90] Y. Gao, H. Li, and Y. Luo, “An empirical study of wearable technology acceptance in healthcare,” Ind. Manage. Data Syst., vol. 115, no. 9, pp. 1704–1723, 2015.
    [91] L. Dunne et al., “The social comfort of wearable technology and gestural interaction,” in Proc. 36th Annu. Int. Conf. IEEE Eng. Med. Biol. Soc., pp. 4159–4162, 2014.
    [92] B. Hensel, G. Demiris, and K. Courtney, “Defining obtrusiveness in home tele-health technologies: A conceptual framework,” J. Amer. Med. Inform. Assoc., vol. 13, pp. 428–431, 2006.
    [93] M. Nyamukuru and K. Odame, “Tiny eats: Eating detection on a microcontroller,” in Proc. IEEE 2nd Workshop Mach. Learn. Edge Sensor Syst., pp. 19–23, 2020.
    [94] J. Amoh and K. Odame, “An optimized recurrent unit for ultra-low-power keyword spotting,” in Proc. ACM Interactive, Mobile, Wearable Ubiquitous Technol., vol. 3, pp. 1–17, 2019.
    [95] I. Jordan and I. Park, “Birhythmic analog circuit maze: A nonlinear neurostimula- tion testbed,” Entropy, vol. 22, p. 537, 2020.
    [96] K. Adam, K. Smagulova, and A. James, “Memristive lstm network hardware architecture for time-series predictive modeling problems,” in Proc. IEEE Asia Pacific Conf. Circuits Syst., pp. 459–462, 2018.
    [97] O. Krestinskaya, K. Salama, and A. James, “Learning in memristive neural network architectures using analog backpropagation circuits,” IEEE Trans. Circuits Syst. I: Regular Papers, vol. 66, pp. 719–732, Feb 2019.
    [98] J. Han, H. Liu, M. Wang, Z. Li, and Y. Zhang, “Eralstm: An efficient reram- based architecture for long short-term memory,” IEEE Trans. Parallel Distrib. Syst., vol. 31, pp. 1328–1342, Jun 2020.
    [99] Z. Zhao, A. Srivastava, L. Peng, and Q. Chen, “Long short-term memory network design for analog computing,” ACM J. Emerg. Technol. Comput. Syst., vol. 15, pp. 1–27, 2019.
    [100] K. Odame, M. Nyamukuru, M. Shahghasemi, S. Bi, and D. Kotz, “Analog gated recurrent unit neural network for detecting chewing events,” IEEE Transactions on Biomedical Circuits and Systems, vol. 16, no. 6, pp. 1106–1115, 2022.
    [101] F. Adil, G. Serrano, and P. Hasler, “Offset removal using floating-gate circuits for mixed-signal systems,” in IEEE Southwest Symposium on Mixed­Signal Design, pp. 190–195, 2003.
    [102] A. Basu, R. Robucci, and P. Hasler, “A low-power, compact, adaptive logarithmic transimpedance amplifier operating over seven decades of current,” IEEE Trans­ actions on Circuits and Systems I: Regular Papers, vol. 54, pp. 2167–2177, Oct 2007.
    [103] C. Schlottmann, C. Petre, and P. Hasler, “Vector matrix multiplier on field programmable analog array,” in IEEE International Conference on Acoustics, Speech, and Signal Processing (ICASSP), pp. 1522–1525, Mar 2010.
    [104] B. A. Minch, “A low-voltage mos cascode bias circuit for all current levels,” in 2002 IEEE International Symposium on Circuits and Systems. Proceedings (Cat. No.02CH37353), pp. III–III, IEEE, 2002.
    [105] B. A. Minch, “Analysis and synthesis of static translinear circuits,” School of Elec­ trical and Computer Engineering, Cornell University, NY, pp. 95–1, 2000.
    [106] J. S. P. Giraldo, S. Lauwereins, K. Badami, and M. Verhelst, “Vocell: A 65-nm speech-triggered wake-up soc for 10- µ w keyword spotting and speaker verification,” IEEE Journal of Solid­State Circuits, vol. 55, no. 4, pp. 868–878, 2020.
    [107] Q. Li, C. Liu, P. Dong, Y. Zhang, T. Li, S. Lin, M. Yang, F. Qiao, Y. Wang, L. Luo, and H. Yang, “Nsfdn: Near-sensor processing architecture of feature- configurable distributed network for beyond-real-time always-on keyword spotting,” IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 68, no. 5, pp. 1892–1905, 2021.
    [108]K. Kim, C. Gao, R. Graça, I. Kiselev, H.-J. Yoo, T. Delbruck, and S.-C. Liu, “A 23μw solar-powered keyword-spotting asic with ring-oscillator-based time-domain feature extraction,” in 2022 IEEE International Solid­ State Circuits Conference (ISSCC), vol. 65, pp. 1–3, 2022.

    無法下載圖示 全文公開日期 2029/08/27 (校內網路)
    全文公開日期 2029/08/27 (校外網路)
    全文公開日期 2029/08/27 (國家圖書館:臺灣博碩士論文系統)
    QR CODE