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研究生： 游東穎
Dong-Ying You
論文名稱： 應用於數據中心之切換式電容轉換器研製
Switched Capacitor Converter for Data Center Application
指導教授： 邱煌仁
Huang-Jen Chiu
口試委員: 龐敏熙
Man-Hay Pong
邱煌仁
Huang-Jen Chiu
謝耀慶
Yao-Ching Hsieh
王建民
Jian-Min Wang
林景源
Jing-Yuan Lin
劉邦榮
Pang-Jung Liu
學位類別： 博士
Doctor
系所名稱： 電資學院 - 電子工程系
Department of Electronic and Computer Engineering
論文出版年： 2024
畢業學年度： 112
語文別： 中文
論文頁數： 155
中文關鍵詞： 諧振切換式電容轉換器 、自適應恆定導通時間 、可控並聯均流 、軟充電 、高效率 、高功率密度 、三階層降壓式飛馳電容轉換器 、電流模式控制 、飛馳電容電壓平衡控制
外文關鍵詞： Ladder-type resonant switched capacitor converter, adaptive constant on-time, controlled current sharing, soft charging, high efficiency, high power density, three-level buck converter, current mode control, flying capacitor voltage-balancing control
相關次數： 點閱：877  下載：122 
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  •  上一筆

    • 本論文針對48 V數據中心電源架構，研製了一款6:1可調壓中間匯流排轉換器(Intermediate Bus Converter, IBC)。為了兼具高效率、高功率密度與縮短產品上市時間，本文鼓勵採用兩級之切換式電容轉換器。非隔離、固定降壓比的轉換器適合作為IBC的後級，以應付大負載，其中具極高功率密度和峰值效率的諧振切換式電容轉換器為首選。因此，本文提出了一款具備高可擴展性的交錯式階梯型架構(Ladder-type Resonant Switched Capacitor Converter, LRSCC)，其優勢還包括減緩傳導性電磁干擾(Electromagnetic Interference, EMI)，允許使用成本效益高的低壓Class II多層陶瓷電容器(Multi-layer Ceramic Capacitor, MLCC)和主動開關來提供設計靈活性。在考慮損耗以及功率級別後，本文實現了3:1 LRSCC硬體原型，並在自適應恆定導通時間控制中導入死區時間調製，以獲得最佳效率和可控的輸出均流能力。至於IBC的前級，則由一款2:1可調壓之三階層降壓式飛馳電容轉換器(Three Level Buck, TLB)來實現。憑藉飛馳電容以及串聯開關的分壓特性，TLB允許使用較低耐壓之主/被動元件、縮小輸出濾波器的需求並提供更高的頻寬。然而，為了避免在連續導通模式(Continuous Conduction Mode, CCM)操作下飛馳電容電壓偏離而導致電路異常的可能性，本文在電流模式控制中引入了飛馳電容電壓平衡機制。最後，本文通過數位信號處理器（Digital Signal Processor, DSP）與現場可程式化邏輯閘陣列(Field Programmable Gate Array, FPGA)的主從架構，實現兩級串機。

    This doctoral dissertation focuses on the development of a 6:1 regulated Intermedi-ate Bus Converter (IBC) tailored for 48V data center power architectures. To achieve a balance between efficiency, power density, and time-to-market, we encourage the use of a two-stage switched capacitor converter. A non-isolated, fixed step-down ratio converter is required as a post-IBC stage to handle large loads, and a resonant switched capacitor converter with extremely high power density and peak efficiency is pre-ferred. Accordingly, this work proposes a highly scalable interleaved Ladder-type Resonant Switched Capacitor Converter (LRSCC) designed to mitigate conductive Electromagnetic Interference (EMI), utilizing cost-effective low-voltage Class II Mul-ti-layer Ceramic Capacitors (MLCCs) and switches to provide design flexibility. A hardware prototype of a 3:1 LRSCC is implemented after careful consideration of losses and power requirements. The design incorporates dead time modulation in the adaptive constant on-time control to optimize efficiency and enable controllable out-put current sharing. For the pre-stage of the IBC, a regulated 2:1 Three-Level Buck (TLB) is implemented. Leveraging the voltage division capabilities of the flying ca-pacitor and series switches, the TLB allows for the use of active/passive components with lower voltage ratings, reduces the need for output filters, and offers the advantage of higher bandwidth. To prevent circuit abnormalities stemming from flying capacitor voltage deviations during Continuous Conduction Mode (CCM), a voltage balancing mechanism for the flying capacitor has been introduced into the current mode control. Finally, this work implements a two-stage cascade system using a master-slave archi-tecture with a Digital Signal Processor (DSP) and a Field Programmable Gate Array (FPGA).

    論 文 摘 要 I ABSTRACT II 誌　　　謝 III 目　　　錄 IV 圖　索　引 VII 表　索　引 XIII 第一章 緒論 1 一. 研究動機與目的 1 二. 章節大綱 8 第二章 高降壓比之諧振切換式電容轉換器 10 一. 階梯形切換式電容轉換器介紹 10 (一). 傳統階梯形切換式電容轉換器(Ladder) 10 (二). 所提出之階梯形切換式電容轉換器(LRSCC) 13 (三). 與其他 RSCC 架構的比較 16 二. 所提出之LRSCC架構的特點與設計要點 26 (一). 改善電流應力和電流均流能力 26 (二). 具有高精細度轉換率的可擴展性 29 (三). 元件容差的抗擾度和控制機制 31 (四). 飛馳電容與諧振電感的最佳選擇 35 (五). 高效率閘極驅動電源設計 39 三. 硬體實作說明 42 (一). 硬體原型介紹 42 (二). 量測結果與硬體性能 47 (三). 與現有先進RSCC的研究比較 54 (四). 傳導電磁干擾(EMI)量測與分析 56 第三章 三階層降壓式飛馳電容轉換器 66 一. 三階層降壓式飛馳電容轉換器介紹 66 二. CCM電路動作分析 69 (一). 責任週期D > 50 %分析 70 (二). 責任週期D < 50 %分析 72 三. 硬體元件參數設計與選用 74 (一). 輸出電感 76 (二). 飛馳電容 77 (三). 輸出電容 79 (四). 輸入電容 80 (五). 功率開關 82 (六). 電壓偵測 84 (七). 電流偵測 85 四. 電流模式控制之小訊號分析 89 (一). 三階層降壓式飛馳電容轉換器之小訊號模型 89 (二). 平均電流模式控制(ACMC)補償設計 98 五. 飛馳電容電壓平衡之小訊號分析 102 (一). 飛馳電容電壓平衡控制(VBC)法 104 (二). 導入飛馳電容VBC於ACMC之小訊號模型 106 (三). 飛馳電容VBC補償設計 113 六. 預充電路與啟動機制 116 七. 硬體實作說明 120 (一). 硬體介紹 120 (二). 量測結果與硬體表現 123 第四章 6:1可調壓中間匯流排轉換器之整合 127 一. 系統韌體規劃 128 (一). SPI通訊協定 128 (二). FPGA (Slave)實現 131 (三). DSP (Master)實現 134 二. 系統硬體串機展示 136 第五章 結論與未來展望 141 一. 結論 141 二. 未來展望 143 參考文獻 145

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