首先，第一部分我們研究class-D n-core振盪器在低電壓工作時具有高電壓擺幅屬性，並使用交叉耦合整流器提供更高的直流輸出。此振盪器實現於台積電矽鍺0.18 μm製程，晶片的面積為1.1×0.88mm2。該振盪器在2.38 GHz提供基頻，並使用三組雙電容交叉耦合和兩顆晶片內部的電感來提升閘極電壓及降低閘極導通電壓，在供應電壓為0.5 V時，輸出電壓為0.87 V。振盪器在供應電壓2V的情況下，觀察高電壓擺幅的影響，發現相位雜訊，頻率，功耗和輸出功率有明顯的下降。
接著，第二部份我們研究一個寬頻帶除二注入鎖定除頻器的除頻範圍屬性，主要的注入功率為-20dBm到10dBm。此除頻器由三路互感耦合諧振器和一組電容交叉耦合與4階RLC共振腔組成以及一個諧波混波MOSFET。第二級電感是由三路徑電感組成可經由MOSFET開關，主要電感是由兩圈單路電感組成，單頻段的鎖頻範圍從4.9GHz到12.71GHz。功率消耗為8.72mW。鎖頻範圍從6.1GHz到12.1GHz。功率消耗為2.6mW。
最後，這篇論文提出一個穩懋氮化鎵 0.25微米製程的振盪器，此電路使用1個GaN HEMT放大器組成一個右手回授振盪器，在供應電壓1 V時，振盪器的電流和功率消耗分別為4.24 mA和4.24 mW。其產生之單端信號輸出頻率為9.171GHz，輸出功率為-10.64 dBm。相位雜訊在1MHz offset為-119.2dBc/Hz，FOM=-192.175 dBc/Hz，晶片面積為2x1 mm2。

First, a class-D n-core oscillator operated at low voltage with high voltage swing and the oscillator uses a cross-coupled rectifier to supply a higher dc output. The chip with an area of 1.1×0.88 mm2 was implemented in the TSMC standard 0.18 μm BiCMOS processes. The oscillator supplies a fundamental at 2.38 GHz and it uses three capacitive cross-coupled pairs with three gate control biases and two on-chip inductors to boost gate voltage for lower gate bias. At the supply voltage of 0.5 V, the converter voltage is 0.87 V. The oscillator was biased at 2 V supply voltage to see the effect of high voltage swing. Degradation in phase noise, frequency, power consumption and output power are found.
Secondly, a wide-band divide-by-2 injection-locked frequency divider (ILFD) in the 0.18 μm CMOS process. The ILFD uses 3-path transformer-coupled resonator and the secondary inductor can be turned on/off by a MOSFET switch. The secondary is made of a three-path inductor and the primary is made of a two-turn single-path inductor. The single-band-like locking range is from 4.9 GHz to 12.71 GHz at the power consumption of 8.72 mW and the locking range is from 6.1 GHz to 12.1 GHz at the power consumption of 2.6 mW. The circuit also shows two non-overlapped locking ranges, which is attributed to the transformer-based 4th order resonator.
Finally, a feedback GaN HEMT oscillator implemented with the WIN 0.25 μm GaN HEMT technology. The oscillator consists of a HEMT amplifier with a right-handed LC feedback network. With the supply voltage of VDD = 1 V, the GaN oscillator-core current and power consumption of the oscillator are 4.24 mA and 4.24 mW, respectively. The oscillator can generate single-ended signal at 9.171 GHz and it also supplies output power -10.64 dBm. At 1MHz frequency offset from the carrier the phase noise is -119.2 dBc/Hz, the FoM of the proposed oscillator is -192.175 dBc/Hz. The die area of the GaN HEMT oscillator is 2×1 mm2.

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