協處理器是用來分擔CPU工作的一種特殊應用的硬體架構，而近年來隨著嵌入式系統的發展，許多協處理器被實現在各種SoC (System-on-Chip) 之上，像是Apple的A14 Bionic chip除了一般目的CPU之外，還有圖形處理器與機器學習使用的矩陣加速器，可以獲得更好的性能表現，但是設計一個協處理器的流程是非常的煩瑣，必須熟悉硬體設計流程與硬體程式的撰寫。
對於協處理器而言，必須要有對應的指令來驅動，RISC-V ISA(RISC-V instruction set architecture)，它是一個開源的指令集架構，它保留了客製化指令的編碼空間，讓使用者非常容易的擴充指令集，添加客製化指令的定義到Compiler之後，Compiler就可以將含有客製化指令的程式編譯成執行檔。
本論文將以RISC-V ISA為基礎，並利用進階綜合工具，將開發協處理器的流程做簡化，讓軟體設計師們不需了解硬體架構該怎麼實作，只需提供C程式之中想用硬體來處理的函式部份做選取，就可以設計出自己的協處理器，並且燒錄到FPGA之上執行，此外，我們將功能整合到IDE，使用者可以用圖形化的方式來操作。

The coprocessor is a hardware architecture used to process some special applications of the main CPU, and with the development of embedded systems in recent years, various coprocessors are implemented on various SoCs (System-on-Chip), such as Apple's A14 Bionic chip, in addition to the general purpose CPU, there are also graphics processors and matrix coprocessor for machine learning. It can get better performance, but the process of designing a coprocessor is also very tedious and requires familiarity with the hardware design process and hardware programming.
For coprocessors, there must be a corresponding instruction to drive, the RISC-V ISA (RISC-V instruction set architecture), which is an open source instruction set architecture, preserves the coding space for custom instructions, allowing users to expand the instruction set easily. you can add custom instructions to your program.
In this paper, we will use RISC-V ISA as the basis, and use advanced synthesis tools to simplify the process of developing a coprocessor, so that software designers don’t need to know how to implement the hardware architecture, but only need to provide a selection of the function in the C program that they want to handle with hardware, and then they can design their own coprocessor and run on FPGA. In addition, we integrate the functions into the IDE so that users can operate graphically.

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