2.5維和3維積體電路之有效的堆疊後的測試技術｜國立臺灣科技大學博碩士論文系統

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研究生：	李淮珉 Huai-Min Li
論文名稱：	2.5維和3維積體電路之有效的堆疊後的測試技術 Efficient Post-Bond Test Techniques for 2.5D and 3D Stacked ICs
指導教授：	呂學坤 Shyue-Kung Lu
口試委員:	郭斯彥 Sy-Yen Kuo 李進福 Jin-Fu Li 王乃堅 Nai-Jian Wang 洪進華 Jin-Hua Hong
學位類別：	碩士 Master
系所名稱：	電資學院 - 電機工程系 Department of Electrical Engineering
論文出版年：	2013
畢業學年度：	101
語文別：	英文
論文頁數：	77
中文關鍵詞：	3維積體電路、矽載板、測試存取機構、可測試性、2.5維積體電路
外文關鍵詞：	3D IC, Interposer, Test Access Mechanism, Testability, 2.5D IC
相關次數：	點閱：260 下載：10
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上一筆

隨著先進製程的快速發展，積體電路的設計變得更加複雜。由於先進製程更容易受到製程瑕疵 (Defect) 的影響，使得晶片的品質與可靠度提升等議題逐漸受到重視。2.5維積體電路 (2.5D IC) 的特性是以矽載板 (Silicon Interposer) 作為平台，將晶片堆疊於矽載板之上，晶片可藉由矽載板內部的TSV連線和RDL與其它晶片作溝通。本論文的目的在於針對以矽載板為基礎的2.5維和3維積體電路 (3D IC) 探討有效的堆疊後的測試技術。為了有效重覆利用功能性連線以作為測試晶片的TAM (Test Access Mechanism)，我們根據並改善先前之研究所提出的技術，進而提出更為有效之矽載板功能性連線的重覆使用策略，使得測試時間減少以及降低運算複雜度，這些策略分別是巨集晶片(Macro Die) 策略、雙向 (Bidirectional) 路徑策略、混合 (Hybrid) 策略以及廣播 (Broadcasting) 策略。先前研究只考量串聯每一個晶片形成一條菊花鏈 (Daisychain)，而巨集晶片策略採用平行的架構。許多晶片集結成一個巨集晶片，再將巨集晶片與其他晶片串成一條菊花鏈。巨集晶片中的所有晶片可同時測試，因此可以降低測試時間，此外因為此方法合併某些TAM，使得TAM的配置方式數目增加，導致演算法找到解的成功率上升。雙向路徑策略則是利用三態緩衝器來變更在一條菊花鏈中反向路徑的方向，使正向及反向路徑皆能傳送測試資料，此方式增加TAM的寬度以致降低測試時間。混合策略則是結合巨集晶片策略和雙向路徑策略。廣播策略是將測試資料廣播到所有的晶片，因此所有晶片可同時測試。實驗結果顯示此論文所提出的策略在成功率、測試長度和演算法複雜度方面均能優於先前之研究。

With the rapid advances of semiconductor technology, the complexity of integrated circuits grows significantly. Three-dimensional integration is considered a promising solution to cure the challenges of performance, power consumption, quality, and reliability issues. The feature of 2.5D ICs is that the dies are stacked on a silicon interposer, and the dies communicate with each other by means of TSV-based interconnects and re-Distribution layers (RDL) in the silicon interposer. This paper aims to investigate the efficient post-bond test technique for the 2.5D ICs with silicon interposer. In order to efficiently reuse the functional interconnects as the parallel TAM (test access mechanism) for testing dies, four strategies including the macro-die strategy, the bidirectional path strategy, the hybrid strategy, and the broadcasting strategy. The macro die strategy merges several dies to form a macro die and then connected to other dies to form a daisy chain for testing. The bidirectional path strategy utilizes tri-state buffers to change the direction of the backward path in a daisy chain during testing such that the TAM width can be broadened. The hybrid strategy combines the features of these two methods. For the broadcasting method, test patterns are broadcasted to all dies simultaneously. Experimental results show that the proposed techniques are better than previous works with respect to the success rate, test length, and algorithm complexity.

摘要	i
Abstract	ii
誌謝	iii
Contents	iv
List of Figures	vi
List of Tables	viii
Chapter 1	Introduction	1
1.1	Motivation	1
1.2	Organization	3
Chapter 2	Background	4
2.1	SOC Technology	4
2.1.1	Overview of SOC	4
2.1.2	IEEE 1500 Standard	5
2.2	3D Integrated Circuit Technologies	6
2.2.1	Overview of 3D Integrated Circuits	6
2.2.2	Enhanced IEEE 1500 Standard for 3D ICs	7
2.3	2.5D Integrated Circuit Technologies	7
2.3.1	Overview of 2.5D Integrated Circuits	7
2.3.2	Testing Concepts for 2.5D Integrated Circuits	9
2.3.2.1	Distributed TAM Architecture	10
2.3.2.2	Daisychain TAM Architecture	11
2.3.2.3	Multiple Daisychain TAM Architecture	12
2.4	Test Architecture Design Algorithm TR-ARCHITECT	14
Chapter 3	Improved Search Strategies	18
3.1	Macro Die Search Methodology	18
3.2	Bidirectional Path Methodology	23
3.3	Hybrid Methodology	27
3.4	Broadcasting Methodology	32
Chapter 4	Experimental Results	36
4.1	Success Rate	36
4.2	Test Length	42
4.3	Computation Time	50
4.4	Hardware Overhead	55
Chapter 5	Conclusions and Future Works	61
5.1	Conclusions	61
5.2	Future Works	62
References	63

                                

[1] R. Patti, “Three-dimensional Integrated Circuits and the Future of System-on-chip Designs,” Proc. of the IEEE, vol. 94, no. 6, pp. 1214–1224, June 2006.
[2] IEEE Computer Society, “IEEE Std 1500TM-2005,” in IEEE Standard Testability Method for Embedded Core-based Integrated Circuits, IEEE, New York, NY, USA, August 2005.
[3] IEEE Computer Society, “IEEE Std 1149.1TM-2001,” in IEEE Standard Test Access Port and Boundary-Scan Architecture, IEEE, New York, NY, USA, June 2001.
[4] E. J. Marinissen, J. Verbree, and M. Konijnenburg, “A Structured and Scalable Test Access Architecture for TSV-Based 3D Stacked ICs,” in Proc. IEEE VLSI Test Symposium (VTS), pp. 269-274, April 2010.
[5] E. J. Marinissen, C. C. Chi, J. Verbree, and M. Konijnenburg, “3D DfT Architecture for Pre-Bond and Post-Bond Testing,” in Proc. IEEE Int’l Conf. on 3D System Integration (3DIC), pp. 1-8, Nov. 2010.
[6] C. C. Chi, E. J. Marinissen, S. K. Goe, and C. W. Wu. “DfT Architecture for 3D-SICs with Multiple Towers,” in Proc. IEEE European Test Symposium (ETS), pp. 51-56, May 2011.
[7] S. K. Goel and E. J. Marinissen, “SOC Test Architecture Design for Efficient Utilization of Test Bandwidth,” ACM Trans. on Design Automation of Electronic Systems, pp. 399-429, Oct. 2003.
[8] C. C. Chi, E. J. Marinissen, S. K. Goel, and C. W. Wu, “Post-Bond Testing of 2.5D-SICs and 3D-SICs Containing a Passive Silicon Interposer Base,” in Proc. IEEE Int’l Test Conf. (ITC), pp. 1-10, Sep. 2011.
[9] C. C. Chi, E. J. Marinissen, S. K. Goel, and C. W. Wu, “Multi-Visit TAMs to Reduce the Post-Bond Test Length of 2.5D-SICs with a Passive Silicon Interposer Base,” in Proc. Asian Test Symposium, pp. 451-456, Sep. 2011.
[10] X. Zhang et al, “Development of Through Silicon Via (TSV) Interposer Technology for Large Die (21x21mm) Fine-Pitch Cu/Low-k FCBGA Package,” in Proc. IEEE Electronic Components and Technology Conf. (ECTC), pp. 305-312, May 2009.
[11] V. S. Rao et al. “TSV Interposer Fabrication for 3D IC Packaging,” in Proc. IEEE Electronic Packaging Technology Conf. (ECTC), pp. 431-437, Dec. 2009.
[12] Y. Y. Ong et al, “Assembly and Reliability of Micro-Bumped Chips with Through-Silicon Vias (TSV) Interposer,” in Proc. IEEE Electronic Packaging Technology Conference (ECTC), pp. 452-458, Dec. 2009.
[13] K. J. Lee, J. J. Chen, and C. H. Huang, “Broadcasting Test Patterns to Multiple Circuits,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 18, no. 12, pp. 1793-1802, Dec. 1999.
[14] E. J. Marinissen, V. Iyengar, and K. Chakrabarty, “A Set of Benchmarks for Modular Testing of SOCs,” in Proc. IEEE Int’l Test Conf. (ITC), pp. 519-528, Baltimore, MD, USA, Oct. 2002.
[15] D. L. Lewis and H. H. S. Lee, “A Scan-Island Based Design Enabling Prebond Testability in Die-Stacked Microprocessors,” in Proc. IEEE Int’l Test Conf. (ITC), pp. 21.2, Oct. 2007.
[16] X. Wu, P. Falkenstern, and Y. Xie, “Scan Chain Design for Three-dimensional Integrated Circuits (3D ICs),” in Proc. Int’l Conf. on Computer Design (ICCD), pp. 208-214, Oct. 2007.
[17] H. H. S. Lee and K. Chakrabarty, “Test Challenges for 3D Integrated Circuits,” IEEE Design&Test of Computers, pp. 26-35, Sep./Oct. 2009.
[18] E. J. Marinissen, “Challenges and Emerging Solutions in Testing TSV-Based 2½D- and 3D-Stacked ICs,” in Proc. IEEE Design, Automation & Test in Europe Conf. & Exhibition (DATE), pp. 1277–1282, Mar. 2012.
[19] S. Y. Huang and Y. S. Fang, “Design of a Low-Power Viterbi Decoder with Multi-Stepping Traceback,” Master Thesis, NTHU, July 2005.
[20] D. I. Oh and S. Y. Hwang, “Design of a Viterbi Decoder with Low Power Using Minimum-Transition Traceback Scheme,” in Electronics Letters, vol. 32, no. 24, pp. 2198-2199, Nov. 1996.
[21] M. Ghoneima, K. Sharaf, H. F. Ragai, and A. E. H. Zekry, “Low power units for the Viterbi decoder,” in Proc. Midwest Symposium on Circuits and Systems, vol. 1, pp. 412-415, Aug. 2000.
[22] X. Liu, and M. C. Papaefthymiou, “Design of a 20-mb/s 256-state Viterbi Decoder,” IEEE Trans. on VLSI Systems, vol. 11, no. 6, pp. 965-975, Dec. 2003.
[23] K. Chakrabarty, “Optimal Test Access Architectures for System-on-a-chip,” in ACM Trans. on Design Automa. of Elect. Syst., pp. 26-49, Jan. 2001.

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