28/38 GHz 雙模頻率合成器｜國立臺灣科技大學博碩士論文系統

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研究生：	江衍霆 Yen-Ting Chiang
論文名稱：	28/38 GHz 雙模頻率合成器 28/38 GHz dual mode frequency synthesizer
指導教授：	陳筱青 Hsiao-Chin Chen
口試委員:	姚嘉瑜 Chia-Yu Yao 邱弘緯 Hung-Wei Chiu
學位類別：	碩士 Master
系所名稱：	電資學院 - 電機工程系 Department of Electrical Engineering
論文出版年：	2019
畢業學年度：	107
語文別：	英文
論文頁數：	84
中文關鍵詞：	第五代行動通訊、雙頻帶整數型頻率合成器、Ka頻段、毫米波積體電路
外文關鍵詞：	Fifth-Generation Mobile Communication, Dual Band Integer-N Frequency Synthesizer, Ka-band, Millimeter-Wave Integrated Circuits
相關次數：	點閱：355 下載：0
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本論文使用TSMC 90奈米CMOS技術實現應用於第五代行動通訊之單晶片28/38 GHz雙頻帶頻率合成器，電壓控制振盪器的可操作頻率範圍為23.5 GHz到28 GHz，相位雜訊在1 MHz的偏移頻率下為-105.57 dBc/Hz ~ -107.08 dBc/Hz，配合除頻器以及混波器，可以使頻率合成器有兩種不同的模式分別對應到操作頻率為28 GHz，通道頻率解析度為281.25 MHz，頻帶內相位雜訊在100 kHz的偏移頻率下為-75.57 dBc/Hz ~ -81.38 dBc/Hz，頻帶外相位雜訊在10 MHz的偏移頻率下為-93.27 dBc/Hz ~ -106.32 dBc/Hz，此時電路功耗為143.16 mW；操作頻率為38 GHz，通道頻率解析度為375 MHz，頻帶內相位雜訊在100 kHz的偏移頻率下為-77.11 dBc/Hz ~ -84.75 dBc/Hz，頻帶外相位雜訊在10 MHz的偏移頻率下為-98.34 dBc/Hz ~ -105.29 dBc/Hz，此時電路功耗為129.64 mW；虛部拒斥比為 17.8 dB ~ 39.73 dB，本地振盪器洩漏拒斥比為 6.07 dB ~ 56.47 dB，鎖定時間為4~6 μs，晶片面積為2.154 mm2。

A 28/38 GHz dual-band frequency synthesizer for 5th generation mobile communication is implemented using TSMC 90-nm CMOS technology. The on-chip VCO achieves the tuning range from 23.5 GHz to 28 GHz, and exhibits the phase noise of -105.57 dBc/Hz~ -107.08 dBc/Hz at 1 MHz offset, from the 23.5 GHz~28 GHz carriers. With dividers and mixers, the 28/38 GHz carrier is synthesized from the VCO output signal in two operation modes, where the synthesizer dissipates 143.16 mW at 28 GHz band with the resolution of 281.25 MHz and the in-band phase noise is -75.57 dBc/Hz ~-81.38 dBc/Hz @ 100 kHz offset, the out-band phase noise is -93.27 dBc/Hz ~-106.32 dBc/Hz @ 10 MHz offset, and 129.64 mW at 38 GHz band with the resolution of 375 MHz and the in-band phase noise is -77.11 dBc/Hz ~-84.75 dBc/Hz @ 100 kHz offset, the out-band phase noise is -98.34 dBc/Hz ~-105.29 dBc/Hz @ 10 MHz offset. The sideband rejection ratio is 17.8 dB ~ 39.73 dB. The LO leakage rejection ratio is 6.07 dB ~ 56.47 dB. The locking time is 4~6 μs. The chip area is 2.154 mm2.

摘要    I
Abstract    II
致謝    III
Contents    IV
List of Figures    VI
List of Tables    X
Chapter1、 Introduction    1
1    Motivation    1
2    Organization    2
Chapter2、 Structure and design of 28/38 GHz Dual-band Frequency Synthesizer for Fifth-Generation Mobile Communications Technology    3
1    The Basic structure of PLL    3
2    Synthesizer Architecture    4
2.1    Phase Frequency Detector (PFD)    5
2.2    Charge Pump (CP)    7
2.3    Loop filter (LPF)    8
2.4    Voltage Controlled Oscillator (VCO)    10
2.5    Miller Divider    12
2.6    Truly Programmable Frequency Divider    13
2.7    28/38 GHz Mixer    15
2.8    Multiplexer (MUX)    16
3    The Consideration of PLL    18
3.1    Phase Noise    18
3.2    Spurs    20
3.3    Locking time    21
3.4    Power down of each band    22
4    Noise analysis of synthesizer architecture    25
5    The EM simulation considerations of the frequency synthesizer    31
Chapter3、Measurement results    39
1    Introduction    39
2    VCO measurement    39
2.1    VCO measurement    39
2.2    VCO measurement results    40
3    Miller frequency divider measurement    43
3.2    Miller frequency divider measurement results    44
4    Mixer+RF MUX measurement    44
4.1    28 GHz band Mixer+RF MUX measurement results    44
4.2    38 GHz band Mixer+RF MUX measurement results    47
5    PLL measurement    50
5.1    PLL measurement    50
5.2    PLL 24 GHz band measurement results    50
5.3    PLL 28 GHz band measurement results    52
5.4    PLL 38 GHz band measurement results    55
5.5    PLL locking time measurement results    58
6    Conclusion    61
Chapter4、Conclusion    65
Reference    66
Appendix A    68


                                

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全文公開日期 2024/02/10 (校內網路)
全文公開日期本全文未授權公開 (校外網路)
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