本論文設計一個具備寬動態範圍與高解析度三維數位至時間轉換器架構，同時提出一個以延遲迴繞法設計的時間至數位轉換器，組成一個具備內建自我測試(Built-In Self Test, BIST)電路的數位至時間轉換器，並成功將整體電路實現於現場可程式化閘陣列(Field Programmable Gate Array, FPGA) Altera Arria 10 開發板。鎖相迴路(Phase-Locked Loop, PLL)以及延遲迴繞(Wrapping)效應為本論文所使用之兩大主要方法，利用PLL之負迴授特性，降低PVT變異帶來的影響，並且利用延遲迴繞，使經過延遲線後產生的延遲相位能夠盡量平均分佈，加上後續的靜態時序分析、量測排序與校正等方法，使延遲相位能更接近理想狀態。
搭配所提出之自動量測方法以大數法則(Law of large numbers)之原理，將量測結果多次加總平均以抑制誤差，並通過不同量測方式將所提出之自我測試電路與市售示波器可達成的量測相互比較，為自動化測試設備(Automatic Test Equipment, ATE)與內建自我測試研發提供嶄新、高效且低成本的實現方式。最終，此高解析度三維數位至時間轉換器，在示波器Tektronix DPO7040測量下，積分非線性誤差(Integral Nonlinearity, INL) 為-1.5~2.9LSB，差分非線性誤差(Differential Nonlinearity, DNL)為-3~3.1 LSB；使用自我測試電路搭配圖形化人機介面化量測，其INL及DNL分別為-2.6~2.7 LSB和-2.9~3.7 LSB；使用自我測試電路搭配pyserial量測以擺脫圖形化人機介面的箝制，其INL及DNL分別為-2.1~2.6 LSB和-3~3.8LSB，效果相近，但可大幅縮短校正時間。

This thesis presents the design of a three-dimensional digital-to-time converter (DTC) with a wide dynamic range and high resolution. Also, it proposes a time-to-digital converter (TDC) implemented with delay line structure to be the built-in self-test (BIST) circuit for the mentioned DTC. The entire circuit is successfully implemented on a field-programmable gate array. Specifically, there are two main techniques employed in this thesis which are the Phase-Locked Loop (PLL) and the delay wrapping mechanism. The PLL utilizes its negative feedback to mitigate the impact of process, voltage, and temperature (PVT) variations. The delay wrapping mechanism is utilized to enhance the resolution. An automatic measurement methodology is proposed leveraging the principle of the Law of Large Numbers to improve the accuracy. A large number of measurements for each DTC input are accumulated and averaged to suppress errors. As a result, to measure the proposed three-dimensional DTC presented using the Tektronix DPO7040 oscilloscope, it exhibits an INL ranging from -1.5 to 2.9LSB and DNL ranging from -3 to 3.1 LSB. By utilizing automated measurement techniques with a graphical user interface (GUI), the INL and DNL are further improved to -2.6 to 2.7 LSB and -2.9 to 3.7 LSB, respectively. Additionally, using the pyserial technique to get rid of GUI, the INL, DNL are improved to -2.1~2.6 LSB, -3~3.8LSB and the measurement time is redcuced substantially.

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