研究生: |
龔柏元 Po-Yuan Kung |
---|---|
論文名稱: |
基於FPGA之單次迭代平行細線化演算法處理系統之設計與實現 Design and Implementation of an FPGA-based Algorithmic Processing System for a One-subiteration Parallel Thinning Algorithm |
指導教授: |
吳乾彌
Chen-Mie Wu |
口試委員: |
陳省隆
Hsing-Lung Chen 陳郁堂 Yie-Tarng Chen 陳漢宗 Hann-Tzong Chern |
學位類別: |
碩士 Master |
系所名稱: |
電資學院 - 電子工程系 Department of Electronic and Computer Engineering |
論文出版年: | 2015 |
畢業學年度: | 103 |
語文別: | 中文 |
論文頁數: | 95 |
中文關鍵詞: | 平行 、細線化 、演算法 |
外文關鍵詞: | FPGA, Parallel, Thinning, Algorithm |
相關次數: | 點閱:326 下載:6 |
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本論文係有關FPGA-based單次迭代平行細線化演算法處理系統之設計與實現,相關研究工作包含下列四大部分。
第一部分為平行細線化演算法之軟體設計;在研究各種平行細線化演算法並考量運算之特性與硬體資源限制後,選擇採用單次迭代平行細線化演算法為本論文研究之標的。
第二部分為設計與實現單次迭代平行細線化演算法處理系統,其主要包含NIOS II CPU、SDRAM(儲存完整的二值化輸入影像及運算結果)、細線化演算法處理器與通訊介面電路,最後把以上各部分整合並以Altera FPGA實現之。
第三部分為撰寫演算法處理系統之相關驅動程式以構成一個驗證系統,並透過NIOS II IDE以JTAG UART控制此硬體電路來驗證其功能。
第四部分為演算法處理系統之驗證與效能評估。
整體而言,本論文係以研究FPGA-based單次迭代平行細線化演算法處理系統為目標,並以Altera FPGA實現之。透過不同的影像測試,證實本論文所發展之演算法處理系統有極佳的效能,其相關之軟硬體整合設計方法,亦可用於其他演算法處理系統之設計與驗證。
This thesis is relevant to the design and implementation of an FPGA-based algorithmic processing system for a one-subiteration parallel thinning algorithm. The research work consists of the following four parts.
The first part focuses on the software design of the parallel thinning algorithm. After studying the various parallel thinning algorithms and considering both the characteristics of the computation and the limitation of hardware resources, a one-subiteration parallel thinning algorithm has been selected as the research target of this thesis.
The second part focuses on the hardware design of an algorithmic processing system for a one-subiteration parallel thinning algorithm. This algorithmic processing system comprises NIOS II CPU, SDRAM (for storing the whole binary input image and computed result), thinning algorithmic processor, and communication interface circuit. Finally, all these parts mentioned above are integrated together and implemented on an Altera FPGA.
The third part is to write the relevant driving programs for the algorithmic processing system to construct a verification system. Meanwhile through NIOS II IDE, JTAG UART is used to control the hardware circuit to verify its functionality.
The fourth part is about the verification and performance evaluation of the algorithmic processing system.
On the whole, the goal of this thesis is to do research on an FPGA-based algorithmic processing system for a one-subiteration parallel thinning algorithm and implement it on an Altera FPGA. After being verified with various kinds of digital images, the algorithmic processing system developed in this thesis has shown fabulous computing performance and the related hardware/software co-design method can also be used in the design and verification process of other algorithmic processing system.
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