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研究生: 莊宗諺
Tsung-Yen Chuang
論文名稱: 利用標準CMOS製程設計積體化背面電極之光伏元件
Design of integrated back-contact solar cells using standard CMOS processes
指導教授: 李三良
San-Liang Lee
口試委員: 洪勇智
Yung-Jr Hung
陳伯奇
Poki Chen
洪儒生
Lu-Sheng Hong
何文章
Wen-Jeng Ho
學位類別: 碩士
Master
系所名稱: 電資學院 - 電子工程系
Department of Electronic and Computer Engineering
論文出版年: 2014
畢業學年度: 102
語文別: 中文
論文頁數: 102
中文關鍵詞: 太陽能積體化背部電極互補式金屬氧化物半導體
外文關鍵詞: solar, IBC
相關次數: 點閱:154下載:7
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  • 本研究利用標準Bulk CMOS製程中高解析度離子佈植與多層金屬連接層的特性,實現積體化背部電極太陽能電池,選擇0.18、0.35μm CMOS製程中的N-well/P-substrate接面區域設計不同對稱結構,觀察太陽能電池的轉換效率變化,並且以場氧化層(Field oxide)做P-N接面之間的電性隔離達到良好的元件隔絕效果。設計的過程中,皆考量到不同標準CMOS製程的限制,並且能夠通過繁複的物理驗證(DRC),由於我們佈局太陽能電池是使用標準電路佈局軟體,因此我們所設計的元件能夠輕易的與其他電路作整合。
    本實驗室已取得三批成果晶片,量測後發現由於原始晶片的基板厚度過厚以及高電阻與較短的載子活期影響下,在1 mW/mm2的980nm紅外光雷射照射後,測得Voc為0.5~0.52V、Jsc為0.068~0.070mA/mm2、轉換效率約4%,僅能產生出0.04mW/mm2的能量,但經過自行磨薄後製程技術對晶片的厚度進行去除,可成功提升Voc到0.54~0.56V、Jsc到0.25~0.27 mA/mm2,轉換效率亦可提升至12~16%左右並產生出0.16mW/mm2的能量,填充因子則維持在0.7~0.85,在文中亦會討論兩家晶圓廠製程結果的不同,提供將來利用此架構的設計做為參考。


    In this thesis, we utilize high resolution doping and multi-layer interconnections provided by standard bulk CMOS processes to implement integrated back-contact solar cells. The diode behavior is realized by parallelly connecting two-dimensional N-well/P-substrate junctions. All heavily-doped contacts are electrically isolated with embedded field oxide in lateral directions to avoid current leakage. The layout of photovoltaic devices within the industry standard electronic design tools is required for the foundry to accept the design for fabrication. Because the processing conditions are optimized for specific design parameters, compliance of the geometric rules is mandatory. Since the on-wafer processing is shared with other customers, as-realized solar cells could be integrated with other microelectronic devices to achieve self-powered system.
    The main roadblocks of CMOS solar cells include its thick substrate, high substrate resistivity, and poor carrier lifetime. Under near-infrared (980 nm) illumination with an intensity of 1 mW/mm2, as-realized CMOS solar cell has a open-circuit voltage of 0.5~0.52 V, a short-circuit current of 0.068~0.07 mA/mm2, and a conversion efficiency of only 4%. Therefore, this device could generate a electrical power of 0.04 mW/mm2. By thinning down the substrate to tens of micrometers, this device could increase its open-circuit voltage and short-circuit current to 0.54~0.56 V and 0.25~0.27 mA/mm2, respectively, leading to a conversion efficiency of 12~16% and a generated power of 0.16 mW/mm2. Thinned solar cells have similar filling factor of 0.7~0.85 as original ones.

    目錄 摘要 1 Abstract 2 致謝 3 目錄 4 圖目錄 6 表目錄 10 第一章 緒論 12 1-1 前言 12 1-2研究動機 12 1-3文獻回顧 16 1-4 論文架構 19 第二章 太陽能電池原理及模擬 21 2-1太陽能電池原理 21 2-2等效電路簡介 22 2-3太陽能電池參數介紹 24 2-4太陽能元件模擬 29 第三章 基於標準CMOS製程架構設計之太陽能電池 35 3-1製程分析與限制 35 3-2 P-N接面佈局設計 38 3-3金屬電極週期佈局設計 44 第四章 量測結果與特性分析 48 4-1下線晶片介紹 48 4-2晶片後製程介紹 55 4-3量測系統架構 59 4-4晶片量測數據分析 62 4-4.1 A晶圓廠0.35μm CMOS IBC太陽能電池 62 4-4.2 A晶圓廠0.18μm CMOS IBC太陽能電池 74 4-4.3 B晶圓廠0.18μm CMOS IBC太陽能電池 87 4-5綜合差異比較 90 第五章 結論 93 5-1成果與討論 93 5-2未來研究方向 94 參考文獻 98

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