本論文探討十二位元之類比數位轉換器 (ADC) 的設計與實現，主要以連續漸進式架構為基礎，為了滿足十二位元的線性度要求，在數位類比轉換器 (Digital-to-Analog Converter, DAC) 中，使用電容交換技術，以得到更好的線性度，另外也包含1個冗餘位元用以補償 DAC 穩定誤差 (Settling Error)，由於得應用在大範圍 (-30°C至120°C) 的溫度感測，漏電是主要的設計難題，因此在靴帶式取樣開關、時脈幫浦…等電路，都需要特殊設計以解決此問題。

本晶片以 TSMC 0.18μm 1P6M CMOS 製程來實現，含 PADs 之晶片面積為 1.09mm2。 其中核心電路面積約為 0.186??2 (420?? × 443??)。SAR ADC之解析度為 12 位元， 取樣率為 1k-S/s，電壓為 0.5V。在常溫之下的佈局後模擬之功耗為 6.64nW，加入雜訊之有效位元為 11.32-bit， FOM 為 2.59 fJ/c-s。

The thesis is mainly aimed at 12-bit successive approximation register(SAR) analog-to-digital converters (ADCs) design. To achieve the 12-bit linearity requirement, the capacitor-swapping switching technique is applied in the DAC that contains 1 redundant bit to compensate for the DAC settling error. Since the ADC will be used in wide-range (-30°C to 120°C) temperature sensing, leakage becomes the main design challenge and the bootstrap sampling switch, clock pump… etc. are all applied to conquer this problem.
This ADC is fabricated in a TSMC 0.18μm 1P6M CMOS process with a chip area of 1.04mm2 including I/O PADs. The core circuit area is around 0.204??2 (461.28?? × 442.66??). The sampling rate is 1k-S/s and the supply voltage is 0.5V. The power consumption of the post-layout simulation at room temperature is 6.64nW and the effective number of bits after voting mode enabled is 11.32-bit and the corresponding FOM is 2.59 fJ/c-s.

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