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研究生: 林暐哲
Wei-Che Lin
論文名稱: 用於低功耗偏置電流源壓控震盪器 與超寬頻之功率放大器設計
Design of Low-Power Current-Biased Voltage-Controlled Oscillator and Ultra-Wideband Power Amplifier
指導教授: 宋峻宇
Jiun-Yu Sung
口試委員: 張勝良
周錫熙
劉效先
學位類別: 碩士
Master
系所名稱: 電資學院 - 電子工程系
Department of Electronic and Computer Engineering
論文出版年: 2023
畢業學年度: 112
語文別: 英文
論文頁數: 100
中文關鍵詞: 震盪器功率放大器低功耗
外文關鍵詞: VCO, PA, UWB
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  • 在RF射頻收發機中,涵蓋了發射機(Tx)、接收機(Rx)、壓控震盪器(VCO)、相位偵測器(PFD)、充電幫浦(CP)、迴路濾波器(LF)、除頻器(FD)與倍頻器(FM)。在鎖相迴路(PLL)中電壓控制震盪器(VCO)扮演著關鍵的角色,隨著科技的進步,各項性能指標也需不斷的更新與改進,低功耗與低雜訊為設計中的主要課題。而在發射機(Tx)中,射頻功率放大器作為最後一端,其效率和線性度指標尤為重要,因此本論文將著重介紹以0.18µm CMOS製程實現低相位雜訊及低功耗電壓控制震盪器(VCO)、與應用於超寬頻功率放大器(PA)之電路設計。第一部分採用一種低電壓、低功耗壓控振盪器 (VCO)。電感電容 (LC) NMOS 交叉耦合 VCO 使用退化源級電感器來改善相位雜訊。開關 FET 在次臨界區域運行,以實現低功耗。VCO使用三匝兩路8字形電感器來抑制干擾噪聲,並使用中心抽頭耦合簡併源電感器來動態提高諧振迴路 Q 因子。兩個電感器配置為低耦合係數變壓器。 8字形電感由兩個3匝O型電感交錯串聯而成。採用台積電 0.18μm CMOS 製程製造的偏置電流源 VCO 的晶片面積為 0.8795 ×0.738 mm2。測得的 VCO 振盪頻率為 2.81 GHz,1 MHz 偏移時的相位雜訊為 - 114.7 dBc/Hz。功耗為 0.272 mW 時,品質因數 (FOM) 為 -189.32 dBc/Hz。第二部分設計了一種電感電容 (LC) NMOS 交叉耦合壓控振盪器 (VCO),具有退化源電感器和用於改善相位雜訊的尾部。VCO使用 2 匝兩路 8 形電感器來抑制干擾噪聲,並使用中心抽頭耦合簡併源電感器來動態提高諧振迴路 Q 因子。兩個源電感器被配置為低耦合係數變壓器。 VCO 的 8 字形電感由 1 個 2 匝 o 形電感絞合而成。採用台積電 0.18μm CMOS 製程製造的電流偏壓 VCO 的晶片面積為 0.833 ×0.782 mm2。測得的 VCO 振盪頻率為 6.979 GHz GHz,1 MHz 偏移時的相位雜訊為 -119.329 dBc/Hz。功耗為 3.875 mW 時,品質因數 (FOM) 為 -189.86 dBc/Hz。
    最後部分設計介紹了一個採用採用 0.18 μm CMOS 製程製造的超寬頻 (UWB) 功率放大器 (PA)。這三個放大器使用壓縮在同一區域的三個不同負載電感器,形成低晶片面積三線,以減少晶片面積。在 5.3 GHz 時,峰值功率增益 S21 為 21.04 dB。頻寬為 3.4 GHz 至 8.2 GHz。所製造的具有三股線的 PA 佔用的面積為 0.928×0.73 mm2,包括輸入/輸出 PAD。由於使用了兩種耦合電感,因此減少了產生的磁場雜訊。 PA 使用三個電感式峰值放大器,其中兩個電阻器與負載電感器串聯。


    In the RF radio frequency transceiver, the blocks include the Transmitter (Tx), the Receiver (Rx), The Voltage Controlled Oscillator (VCO), the Phase Director (PFD), the Charge Pump (CP), and the Loop Filter (LF), Frequency Divider (FD) and Frequency Multiplier (FM). The voltage controlled oscillator (VCO) plays a key role in the phase locked loop (PLL). With the advancement of technology, various performance indicators also need to be constantly updated and improved. Low power consumption and low noise are the main considerations in the design. In the transmitter (Tx), the RF power amplifier is the last step, and its efficiency and linearity indicators are extremely important. Therefore, this paper will adopt a system to introduce a low-phase noise and low-power voltage-controlled oscillator using a 0.18μm CMOS process. (VCO), and circuit design for evaluating ultra-wideband power amplifier (PA).The first part presents the design of a low-voltage and low-power voltage-controlled oscillator (VCO). An inductance-capacitance (LC) NMOS cross-coupled VCO uses a degenerated source inductor for phase noise improvement. The switching FET operates in a subthreshold region for low-power operation. The VCO uses a 3-turn two-lobe 8-shaped inductor for interference noise suppression and a center-tapped coupled degenerated-source inductor to dynamically boost the tank Q factor. The two inductors are configured as a low-coupling coefficient transformer. The 8-shaped inductor consists of two 3-turn O-shaped inductors in a twisted series. The die area of the current-biased VCO fabricated in the TSMC 0.18μm CMOS process is 0.8795 ×0.738 mm2. The measured oscillation frequency of the VCO is 2.81 GHz, and the phase noise at 1 MHz offset is - 114.7 dBc/Hz. and the figure of merit (FOM) is -189.32 dBc/Hz at the power consumption of 0.272 mW.
    The second part introduces the design of an inductance-capacitance (LC) NMOS cross-coupled voltage-controlled oscillator (VCO) with a degenerated source inductor and a tail for phase noise improvement. The VCO uses a 2-turn two-lobe 8-shaped inductor for interference noise suppression and a center-tapped coupled degenerated-source inductor to boost the tank Q factor dynamically. The two source inductors are configured as a low-coupling coefficient transformer. The VCO-core 8-shaped inductor consists of one 2-turn O-shaped inductor in a twisted series. The die area of the current-biased VCO fabricated in the TSMC 0.18μm CMOS process is 0.833 ×0.782 mm2. The measured oscillation frequency of the VCO is 6.979 GHz GHz, and the phase noise at 1 MHz offset is -119.329 dBc/Hz. and the figure of merit (FOM) is -189.86 dBc/Hz at a power consumption of 3.875 mW.
    The third part introduces a new 8-shaped transformer used in Ultra-Wideband Transmitter. The transmitter utilizes a new 8-shaped transformer, which consists of a series combination of a 2:1 O-shaped transformer and a 1:2 O-shaped transformer. The transformer is formed by two 2-lobe 8-shaped inductors. Its performance and functionality are demonstrated in an on-off keying (OOK) ultra-wideband (UWB) transmitter. The UWB transmitter is specifically designed for applications in UWB communications and operates at a frequency of 3.38 GHz. The design of the UWB transmitter is fabricated using the TSMC 0.18μm CMOS process, and the resulting die area of the transmitter is measured to be 1.110×0.963mm2.

    摘要 I Abstract III 致謝 V Table of Contents VI List of Figures VIII List of Tables XIV Chapter 1 Introduction 1 1.1 Research Background 1 1.2 Thesis Organization 4 Chapter 2 Principles and Design Considerations of Voltage-Controlled Oscillators 6 2.1 Introduction 6 2.2 The Oscillators Theory 8 2.2.1 Feedback Oscillators (Two ports) 9 2.2.2 One port Resonator and Negative Resistance 11 2.3 Category of Oscillators 15 2.3.1 Ring Oscillator 15 2.3.2 LC-Tank Oscillator 19 2.4 Design Principles of Voltage-Controlled Oscillator 24 2.4.1 Characteristics of a Voltage-Controlled Oscillator 25 2.4.2 Phase Noise 28 2.4.3 Quality Factor 34 Chapter 3 Low-Power Current-Biased Voltage-controlled Oscillator 36 3.1 Introduction 36 3.2 Circuit Design 38 3.3 Experimental 45 Chapter 4 Complementary Voltage-controlled Oscillator with Hybrid Source Inductors 58 4.1 Introduction 58 4.2 Circuit Design 59 4.3 Experimental 66 Chapter 5 Area-efficient Ultra-wide-band CMOS Power Amplifier with a Hybrid Trifilar 73 5.1 Introduction 73 5.2 Circuit Design 75 5.3 Experiment of the UWB Power Amplifier 82 Chapter 6 Conclusions 94 References 96

    [1] B. Razavi, RF Microelectronics, Upper Saddle River, NJ: Prentice Hall, 1998.
    [2] N. M. Nguyen and R. G. Meyer, "Start-up and frequency stability in high-frequency oscillators," in IEEE Journal of Solid-State Circuits, vol. 27, no. 5, pp. 810-820, May 1992, doi: 10.1109/4.133172.
    [3] B. Razavi, Design of Integrated Circuits for Optical Communications, Mc Graw Hill.
    [4] B. Razavi, Design of Analog CMOS Integrated Circuits, Mc Graw Hill, 2001.
    [5] A. Hajimiri and T. H. Lee, “Design issues in CMOS differential LC oscillators,” IEEE J. Solid-State Circuits, vol. 34, no. 5, pp. 717–724, May 1999.
    [6] E. Hegazi, H. Sjoland, and A. A. Abidi, “A filtering technique to lower LC oscillator phase noise,” IEEE J. Solid-State Circuits, vol. 36, no. 12, pp. 1921–1930, Dec. 2001.
    [7] B, Jafari and S. Sheikhaei, “Phase noise reduction in a CMOS LC cross-coupled oscillator using a novel tail current noise second harmonic filtering technique,” Microelectron J. 2017; 65: 21-30. doi:10.1016/j.mejo.2017.05.003
    [8] N. N. Tchamov and N. T. Tchamov, “Technique for flicker noise upconversion suppression in differential LC oscillators,” IEEE Trans. Circuits Syst., II, Exp. Briefs, vol. 54, no. 11, pp. 959–963, Nov. 2007.
    [9] H. Lee and S. Mohammadi, "A subthreshold low phase noise CMOS LC VCO for ultra low power applications," IEEE Microwave and Wireless Components Lett., vol.17, no.11, pp.796-798, Nov. 2007.
    [10] Q. Zeng et al., "A 23.9-30.5 GHz harmonic extraction VCO with high subharmonic suppression," 2022 IEEE MTT-S International Microwave Workshop Series on Advanced Materials and Processes for RF and THz Applications (IMWS-AMP), Guangzhou, China, 2022, pp. 1-3, doi: 10.1109/IMWS-AMP54652.2022.10107037.
    [11] H. -C. Lee, S. -L. Jang and R. -X. Yang, "Low power CMOS VCO using an 8-shaped transformer," 2023 IEEE 23rd Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems, Las Vegas, NV, USA, 2023, pp. 19-21, doi: 10.1109/SiRF56960.2023.10046255.
    [12] H. -C. Lee, S. -L. Jang and D. -L. Wang, "Voltage- and current-mode ÷3 injection-locked frequency divider," 2023 International VLSI Symposium on Technology, Systems and Applications (VLSI-TSA/VLSI-DAT), Hsinchu, Taiwan, 2023, pp. 1-2, doi: 10.1109/VLSI-TSA/VLSI-DAT57221.2023.10134367.
    [13] H.-C. Lee, S.–L. Jang, H.‐W. Liu, L. Y. Chen,” Divide-by-2 injection-locked frequency divider exploiting an 8-shaped inductor,” Microw Opt Technol Lett. vol. 63, no. 4 pp.1024-1028, April. 2020.
    [14] Z. Zong, G. Mangraviti, and P. Wambacq, “Low 1/ f3 noise corner LC-VCO design using flicker noise filtering technique in 22 nm FD-SOI,” IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 67, no. 5, pp. 1469–1480, May 2020, doi: 10.1109/TCSI.2020. 2970267.
    [15] Z. Zong, G. Mangraviti, and P. Wambacq, “Low 1/ f3 noise corner LC-VCO design using flicker noise filtering technique in 22 nm FD-SOI,” IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 67, no. 5, pp. 1469–1480, May 2020, doi: 10.1109/TCSI.2020. 2970267.
    [16] Y.‐H. Chang and J.‐F. Liang, “CMOS voltage‐controlled oscillator using inductive dual‐balance source degeneration,” Electron. Lett. 58(25), 946–948 (2022).
    [17] R.-L. Wang, M.-C. Lin, Y.-J. Tzeng, C.-F. Yang and Y.-S. Lin, "A switched-capacitor current-reused VCO with symmetrical differential outputs," 2008 Asia-Pacific Microwave Conference, Hong Kong, China, 2008, pp. 1-4, doi: 10.1109/APMC.2008.4957869.
    [18] M.-D. Wei, S.-F. Chang, and S.-W. Huang, “An amplitude-balanced current-reused CMOS VCO using spontaneous transconductance match technique,” IEEE Microw. Wireless Compon. Lett., vol. 19, no. 6, pp. 395–397, Jun. 2009.
    [19] S. Oh, K.-S. Seo and J. Oh, "Low phase noise concurrent dual-band (5/7 GHz) CMOS VCO using gate feedback on nonuniformly wound transformer," IEEE Microw. Wireless Compon. Lett., vol. 31, no. 2, pp. 177-180, Feb. 2021.
    [20] J. Lee and B. Razavi, “A 40-GHz frequency divider in 0.18μm CMOS technology,” IEEE J. Solid-State Circuits, vol. 39, pp. 594-601, Apr. 2004.
    [21] E. Hegazi, H. Sjoland, and A. A. Abidi, “A filtering technique to lower LC oscillator phase noise,” IEEE J. Solid-State Circuits, vol. 36, no. 12, pp. 1921–1930, Dec. 2001.
    [22] A. Hajimiri and T. H. Lee, “Design issues in CMOS differential LC oscillators,” IEEE J. Solid-State Circuits, vol. 34, no. 5, pp. 717–724, May 1999.
    [23] N. N. Tchamov and N. T. Tchamov, “Technique for flicker noise upconversion suppression in differential LC oscillators,” IEEE Trans. Circuits Syst., II, Exp. Briefs, vol. 54, no. 11, pp. 959–963, Nov. 2007
    [24] Q. Zeng et al., "A 23.9-30.5 GHz harmonic extraction VCO with high subharmonic suppression," 2022 IEEE MTT-S International Microwave Workshop Series on Advanced Materials and Processes for RF and THz Applications (IMWS-AMP), Guangzhou, China, 2022, pp. 1-3, doi: 10.1109/IMWS-AMP54652.2022.10107037.
    [25] Z. Zong, G. Mangraviti, and P. Wambacq, “Low 1/ f3 noise corner LC-VCO design using flicker noise filtering technique in 22 nm FD-SOI,” IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 67, no. 5, pp. 1469–1480, May 2020, doi: 10.1109/TCSI.2020. 2970267.
    [26] Y.‐H. Chang and J.‐F. Liang, “CMOS voltage‐controlled oscillator using inductive dual‐balance source degeneration,” Electron. Lett. 58(25), 946–948 (2022).
    [27] R.-L. Wang, M.-C. Lin, Y.-J. Tzeng, C.-F. Yang and Y.-S. Lin, "A switched-capacitor current-reused VCO with symmetrical differential outputs," 2008 Asia-Pacific Microwave Conference, Hong Kong, China, 2008, pp. 1-4, doi: 10.1109/APMC.2008.4957869.
    [28] M.-D. Wei, S.-F. Chang, and S.-W. Huang, “An amplitude-balanced current-reused CMOS VCO using spontaneous transconductance match technique,” IEEE Microw. Wireless Compon. Lett., vol. 19, no. 6, pp. 395–397, Jun. 2009.
    [29] S. Oh, K.-S. Seo and J. Oh, "Low phase noise concurrent dual-band (5/7 GHz) CMOS VCO using gate feedback on nonuniformly wound transformer," IEEE Microw. Wireless Compon. Lett., vol. 31, no. 2, pp. 177-180, Feb. 2021.
    [30] D. Fathi and A. Nejad, "Ultra-low power, low phase noise 10 GHz LC VCO in the subthreshold regime," Circuits and Systems, Vol. 4 No. 4, 2013, pp. 350-355.
    [31] J. -S. Syu, C. Meng and G. -W. Huang, "SiGe HBT quadrature VCO utilizing trifilar transformers," 2008 IEEE Asian Solid-State Circuits Conference, Fukuoka, Japan, 2008, pp. 465-468, doi: 10.1109/ASSCC.2008.4708828.
    [32] Y. Chang, Y. Wang, and H. Wang, “A K-band high-OP1d B common drain power amplifier with neutralization technique in 90-nm CMOS technology,” IEEE Microw. Wireless Compon. Lett., vol. 29, no. 12, pp. 795–797, Dec. 2019.
    [33] G. Singh et al., “An IR-UWB IEEE 802.15.4z compatible coherent asynchronous polar transmitter in 28-nm CMOS,” IEEE J. Solid-State Circuits, vol. 56, no. 12, pp. 3799–3810, Dec. 2021.
    H. Kim, S. Ryu, Y. Chung, J. Choi, and B. Kim, “A low phase-noise
    CMOS VCO with harmonic tuned LC tank,” IEEE Trans. Microw. Theory
    Techn., vol. 54, no. 7, pp. 2917–2923, Jul. 2006
    [34] R-L Wang, Y-K Su and C-H Liu; “3~5 GHz Cascoded UWB Power Amplifier,” Proc. IEEE Asia Pacific Conference on Circuits and Systems, pp 367-369, 2006.
    [35] Sew-Kin Wong, et al., “High Efficiency CMOS Power Amplifier for 3 to 5 GHz Ultra-Wide band (UWB) Application,” IEEE Transactions on Consumer Electronics, vol. 55, no. 3, 2009.
    [36] S. Z. Murad, R. K. Pokharel, A. Galal, R. Sapawi, H. Kanaya, and K. Yoshida, “An excellent gain flatness 3.0–7.0 GHz CMOS PA for UWB applications,” IEEE Microw. Wireless Compon. Lett., vol. 20, no. 9, pp. 510–512, Sep. 2010.
    [37] H.-W. Chung, C.-Y. Hsu, C.-Y. Yang, K.-F. Wei, and H.-R. Chuang, “A 6–10 GHz CMOS power amplifier with an inter-stage wideband impedance transformer for UWB transmitters,” in Proc 38th Eur. Microw. Conf., Oct. 27–31, 2008, pp. 305–308.
    [38] C. Lu, A.-V. Pham, and M. Shaw, “A CMOS power amplifier for fullband UWB transmitters,” in Proc. IEEE Radio Freq. Integr. Circuit (RFIC) Symp., Jun. 11–13, 2006, p. 400.

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