應用於低軌道衛星通訊接收端之K-頻帶主動式七位元數位控制向量合成相移器已實現並使用台積電 TSMC 90-nm CMOS製程. 相移器由正交全通濾波器和一個8位元數位類比轉換器（IDAC）偏壓的類比向量加法器組成。本研究探討了相移器的相位精度受到IDAC的解析度和加法器I/Q輸入的相位誤差影響。電晶體閘極存在漏電流的問題已解決，來提高偏壓電路的準確性，使得8位元IDAC可以達到INL為-0.26至0.13 LSB, DNL為-0.013至0.007 LSB。對於阻抗匹配，將匹配元件電感設計在QAF和加法器之間，並且分析了負載效應對於加法器的輸入振幅誤差和輸入相位誤差的影響。根據測量結果，相移器的RMS相位誤差為0.17°至0.19°，RMS振幅誤差為1.11至1.9 dB。在17-21 GHz頻段內，平均增益為-3.31至1.28 dB。晶片核心尺寸為0.76 mm^2。相移器在1.2 V供應電壓下總功耗為8.4 mW。

An active type 7-bit vector-sum phase shifter (VSPS) with digital control is designed and implemented using TSMC 90-nm CMOS technology for K-band (17-21 GHz) low earth orbit satellite communication. The phase shifter consists of a resonance-based quadrature all-pass filter and an analog vector adder that is biased with 8-bit current digital-to-analog converters (IDACs). In this work, how the phase accuracy of the phase shifter is influenced by the resolution of the current DAC and phase error of the adder I/Q inputs is investigated. The leakage current issue has been resolved to improve the accuracy of bias circuits so that the 8-bit IDAC can achieve the INL of -0.26 ~ 0.13 LSB and DNL of -0.013 ~ 0.007 LSB. For impedance matching, inductors are inserted between the QAF and the adder, and the input amplitude error and the input phase error of the adder are formulated to consider the impact of the loading effect. According to measurement results, the phase shifter exhibits the RMS phase error of 0.17° to 0.19° and the RMS amplitude error of 1.11 to 1.9 dB. The average gain is -3.31 ~ 1.28 dB over the 17-21 GHz. The core chip size is 0.76 mm^2. The phase shifter dissipates the total power consumption of 8.4 mW from the 1.2 V supply voltage.

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