近年來在x86與arm兩大的陣營的商業發展下，主流市場的指令集架構(ISA, instruction set archicture)大致被兩者占據，在家用電腦市場中以Intel的x86佔據最大份額，在手機、平板中則被ARM指令集架構所佔據。而在這樣的環境下，出現了以開放原始碼的規範提出的指令集架構 RISC-V ，嘗試在這樣的市場突出重圍，RISC-V在現今成為目前社群最為活躍的指令集架構。

衡量軟硬體的效能是開發者在開發時需要考量的一大面向，而測量程式的效能時，使用實體的硬體直接測量是一種方式，然而硬體修改成本較高時間也較久，使用軟體的模擬器是一種衡量程式效能的方案。

在本篇論文中，我們實作32位元的RISC-V G擴充指令集在SimpleScalar之上，使其可以藉由SimpleScalar 模擬器來模擬執行RISC-V指令集，並且使用RISC-V版本的gcc編譯的SPEC2000的benchmark 來進行實驗，藉由我們提出的工具，讓未來的開發者要使用到RISC-V指令集做效能評估時，可以使用我們的工具來進行。

In recent years, under the commercial development of the two major camps of x86 and ARM, the instruction set architecture (ISA, instruction set archicture) of the mainstream market has been roughly occupied by the two. Intel's x86 has the largest share in the home computer market. The tablet is occupied by the ARM instruction set architecture. In such an environment, the instruction set architecture RISC-V proposed by the open source code specification has emerged. RISC-V is now the most active instruction set architecture in the community.

Measuring the performance of software and hardware is a major aspect that developers need to consider during development. When measuring the performance of a program, direct measurement using physical hardware is a method. However, hardware modification costs higher and takes longer. Software simulators are a measure of program performance.

In this paper, we implement the 32-bit RISC-V G extended instruction set on SimpleScalar, so that it can use the SimpleScalar simulator to simulate the execution of the RISC-V instruction set. We use the RISC-V version of gcc to compile SPEC2000 benchmark for experiments. With our proposed tools, future developers can use our tools when they want to use the RISC-V instruction set for performance evaluation.

[1] Asanović, K. and Patterson, D. Instruction Sets Should Be Free: The Case For RISC-V (EECS-2014-146), August 6, 2014.

[2] Todd Austin, Eric Larson, and Dan Ernst. SimpleScalar: An infrastructure for computer system modeling. IEEEComputer, 35(2):59-67 2002

[3] SPEC: Standard Performance Evaluation Corporation.
http://www.spec.org, Sep. 2000

[4] The RISC-V Instruction Set ManualVolume I: Unprivileged ISA
https://riscv.org/specifications/ Dec. 2019

[5] The gem5 simulator
http://www.gem5.org/

[6] QEMU RISC-V
https://github.com/riscv/riscv-qemu

[7] Spike, a RISC-V ISA Simulator
https://github.com/riscv/riscv-tools
[8] “RISC-V Offers Simple, Modular ISA,” D. Kanter, The Linley Group MICROPROCESSOR report, March 2016.

[9] Karthikeyan Sankaralingam, Ramadass Nagarajan, Stephen W. Keckler “SimpleScalar Simulation of the PowerPC Instruction Set Architecture” February 2001

[10] GNU toolchain for RISC-V, including GCC
https://github.com/riscv/riscv-gcc

[11] RISC-V ELF psABI specification
https://github.com/riscv/riscv-eabi-spec

[12] Rangeen Basu Roy Chowdhury, Anil Kumar Kannepalli, Eric Rotenberg “FabScalar-RISCV” Jane 2015