三維積體電路將各層的裝置整合在一起後，導致電路嚴重無法散熱的問題，進而使得整體電路可靠度的降低；可靠度的降低不僅僅造成電路的損害還會造成不可預期的錯誤或損失。
由於電路散熱及可靠度的問題日趨嚴重，所以本篇論文提出了適用於三維積體電路設計的全新型態訊號導通孔（矩形訊號導通孔以及一般型態訊號雙導通孔）技術，並且使用模擬退火的機制來插入此二種訊號導通孔。
先前的研究指出在一定程度下，當訊號導通孔越多，可靠度會越高，但是卻會造成越大的面積。因此，適當地取捨訊號導通孔的數量、可靠度及面積是相當重要的，我們的研究在考量上述取捨中插入適當的訊號導通孔，此外也將散熱導通孔插入處理完之溫度導向平面規劃。有了這些規劃，我們相信此研究能夠確保電路更為可靠。
實驗結果顯示我們的研究可以有效的將單一訊號導通孔改善為矩形訊號導通孔以及一般型訊號雙導通孔達百分之八十以上；再加上，我們可以用極少數量的散熱導通孔即能改善整體電路的溫度至攝氏八十度左右。

Vertical integration of layers in a 3D IC exacerbates thermal problem especially for reliability degradation. Low reliability can not only damage the whole circuits but also occur unexpected performance loss. In this thesis, we conduct the SA engine with rectangle-STSVs and double-STSVs for improving reliability. The earlier research indicates that the more STSVs a chip has, the better the reliability is. However, it also implies a larger area. Therefore, we develop a methodology to manipulate thermal-aware floorplan with the tradeoff among the number of STSVs, reliability, and area of a chip. Moreover, we manage our manipulated floorplan with precise thermal model for TTSVs insertion at via channel. Experimental results show that more than 80% of single-STSVs can be replaced by rectangle-STSVs or double-STSVs, thereby improving reliability. Furthermore, temperature can be maintained around 80℃ with minimal TTSVs after inserting TTSVs.

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