本文為針對極化碼(Polar code)置信傳播列表(Belief Propagation List)解碼器提出新式超大型積體電路(VLSI)硬體設計與實作，設計上以減少硬體消耗為主。藉由重複利用計算單元進行運算可有效降低硬體成本外還可以減少計算過程中的硬體閒置，利用架構優勢使循環利用的計算單元得以實現高度的平行化計算，藉此達成在不犧牲時間成本的條件下提高解碼器計算準確度。本文使用Matlab建構演算法開發與驗證模擬，並以C實現與演算法相對應環境，達到與硬體開發平台溝通驗證，硬體部分使用Verilog進行設計並實現於Virtex7 FPGA 開發板進行驗證，並且將此電路再透過TSMC 40nm CMOS製程進行硬體實現。

This paper proposes the hardware design and practice of the new very-large-scale integration (VLSI) for the Polar Code Belief Propagation List (BPL) decoder, which is designed to reduce hardware consumption. By reusing the cell to perform operations, hardware cost can be effectively reduced, but also reduce hardware idleness in the calculation process, the use of architectural advantages to enable recycled computing units to achieve a high degree of parallelization calculation, so as to achieve the solution without sacrificing the cost of time to improve the accuracy of decoder calculations. In this paper, Matlab construction algorithm is used to develop and verify simulation, and C implementation and algorithm corresponding environment, to achieve communication and verification with the hardware development platform, hardware part of the use of Verilog design and implementation in the Virtex7 FPGA development board for verification, and this circuit through the TSMC 40nm CMOS for hardware implementation.

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