近幾年無線通訊系統非常蓬勃的發展，系統技術也是日新月異，多種調變技術陸續被提出。目前最廣泛使用在無線通訊系統中的就是正交分頻多工 (OFDM)，它要求子載波間必須要具有正交性，且需求高精密度的同步電路，所以他的頻譜效率較差。而廣義分頻多工(GFDM)具有較低的帶外輻射功率(OOB)，較高的靈活性，且循環前綴(cyclic prefix, CP)的使用數也較少，因此，綜合以上所述，GFDM成為未來5G所討論的調變候選技術之一。
本篇論文基於超大型積體電路實現廣義分頻多工系統中的最小平方誤差(MMSE)接收器，並有效的利用分時多工架構設計電路，達成低複雜度與可調適之設計。本論文使用奇異值分解處理通道矩陣，並利用其設計均衡器，解調器利用快速傅立葉轉換(FFT)化簡了矩陣運算的複雜度，在這裡我們提出了一個新的接收器資料處理流程，並且針對流程中記憶體讀寫過程，進行簡化並合併。本文基於台積電90奈米製程的環境下實現，根據合成結果顯示，操作在207百萬赫茲的工作頻率下，消耗的596.4K個邏輯閘，並且與已知的FPGA實現結果相比，本論文達成了低複雜度與可調適的接收器電路結果。

This thesis presents a configurable and low-complexity very-large-scale integration (VLSI) architecture of a minimum mean square error (MMSE) generalized frequency division multiplexing (GFDM) receiver. The receiver is comprised of two components, an equalizer, and a demodulator. The equalizer applies singular value decomposition (SVD) to simplify the calculations. The demodulator is composed of a fast Fourier transform (FFT), controller, memory, dispatcher, and multiplier. The FFT algorithm requires the bit-reversal permutation to obtain the correct sequence. Aiming to reduce the additional circuit area and latency, our architecture simultaneously processes the bit-reversal permutation and a shuffle permutation in the data processing flow. Moreover, our proposed design integrates a complex multiplier and FFT. It effectively reduces the area to achieve better performance. Therefore, we developed a suitable VLSI architecture based on a data processing flow. The two-stage receiver greatly reduces the area complexity of the design. On this new hardware, we adopt a time-sharing architecture and radix-2 single-path delay feedback (SDF) FFT architecture to reduce complexity. The processing module of the hardware architecture is designed for varying configurations of parameters, subcarriers, and subsymbols. The proposed design is realized in a Taiwan Semiconductor Manufacturing Company (TSMC) 90 nm technology, occupying a total gate equivalent of 707.83 kGEs at an operating frequency of approximately 207 MHz. Hardware test results show that, as expected, our design reduces its area complexity considerably compared with prior works.

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