隨著科技和無線通訊系統的迅速發展，頻率合成器（或稱鎖相迴路PLL：Phase Locked Loop）在RFIC（無線射頻集成電路）中擔任著至關重要的角色。PLL的內部電路包含了相位偵測器（PFD）、電荷泵（CP）、環形濾波器（LF）、壓控震盪器（VCO）以及除頻器（FD）等組件。在高頻率應用中，壓控震盪器（VCO）成為PLL中最為關鍵的元件，它必須在保持高傳輸速度的同時，實現低功耗、低相位雜訊，並擁有更廣泛的工作範圍。

首先，我們將介紹一個利用電流回收的電路，包括一個VCO、一個頻率倍增器和一個達林頓放大器。頻率倍增器和達林頓放大器堆疊在VCO之上。電流重複使用的頻率倍增器（FD）電路接收來自電壓控制振盪器（VCO）的輸入信號，將較低頻率的振盪器與頻率倍增器（FD）串聯起來。頻率倍增器利用平衡的差動輸入來驅動FET對，消除輸出端的基波和奇次諧波。然而，平衡的頻率倍增器通常具有較低的轉換增益，因此需要一個放大器來放大輸出功率。整個電路的功耗為8.2毫瓦，輸出頻率範圍從15.773 GHz到15.043 GHz。在1MHz偏移頻率下的相位雜訊為-105.13 dBc/Hz，振盪頻率為15.988 GHz，圖中品質（FOM）值為-173.76 dBc/Hz，晶片的面積為1.07×1.19平方毫米。本章節與台大電子所博士生 鄭盛仁 共同開發。

第4章
接下來，我們將介紹八字形電感的集中式電路模型，以及帶有八字形電感的耦合電感的噪聲耦合模型。將磁場耦合噪聲電路模型與電感佈局所得的結果進行驗證。從耦合噪聲模型中，我們展示了磁場耦合的物理見解。
第5章
接下來，讓我們介紹兩個重要的EMC（電磁兼容性）設計問題：基板噪聲干擾和磁場耦合。本章介紹了耦合八角形電感的模擬和建模的耦合噪聲結果。首先，它模擬了兩個耦合的八角形電感的磁場耦合噪聲，以了解磁場耦合的物理見解。磁場耦合噪聲電路模型與電感佈局的結果進行了驗證。單端模型然後擴展到差動模型。

第6章
倒數第二章介紹了在0.18 μm CMOS工藝中實現的一個新型的VCO設計，具有一個單圈八字形電感。實現的VCO顯示了由變容器偏壓控制的4.5 GHz到5.31 GHz的振盪頻率。計算的FOM為-193.65 dBc/Hz。整個芯片佔用了0.6887×1.1538平方毫米的小面積。成功的電感設計將進一步推動電感佈局的設計。

第7章
最後，電感校準電路的應用可以幫助在不同的環境條件下保持VCO的一致性性能，提高系統的可靠性和信號質量。基於前幾章討論的八字形電感的集中式電路模型以及在0.18 μm CMOS工藝中實現的單圈八字形電感的VCO設計，我們將把八字形電感的等效模型納入其電路中。

First, we will introduce a circuit that utilizes current recycling, consisting of a VCO, a frequency multiplier, and a Darlington amplifier. The frequency multiplier and the Darlington amplifier are stacked on top of the VCO. The current-reusing frequency multiplier (FD) circuit receives the input signal from the Voltage-Controlled Oscillator (VCO), serially connecting the lower-frequency oscillator with the frequency multiplier (FD). The frequency multiplier utilizes balanced differential input to drive FET pairs, eliminating the fundamental and odd-order harmonics at the output. However, balanced frequency multipliers typically have lower conversion gain, necessitating an amplifier to amplify the output power. The overall circuit power consumption is 8.2 milliwatts, with an output frequency ranging from 15.773 GHz to 15.043 GHz. The phase noise at a 1MHz offset frequency is -105.13 dBc/Hz, with an oscillation frequency of 15.988 GHz and a Figure of Merit (FOM) value of -173.76 dBc/Hz. The chip's area is 1.07×1.19 mm². This chapter was co-developed with Dr. Sheng-Jen Cheng, a Ph.D. from the Department of Electrical Engineering at National Taiwan University.

Next, the lumped circuit model of the 8-shape inductor is introduced, along with the noise coupling model of coupled inductors featuring 8-shape inductors. The magnetic field coupling noise circuit model is verified against the results obtained from the inductor layout. From the coupling noise models the physics insight of magnetic field coupling is illustrated.

Next, let's introduce two important EMC (Electromagnetic Compatibility) design issues: substrate noise interference and magnetic field coupling. This chapter presents the simulation and modeled coupling noise results from coupled octagonal inductors. First, it models the magnetic field coupling noise of two coupled octagonal inductors to see the physics insight of magnetic field coupling. The magnetic field coupling noise circuit model is verified against the results from the inductor layout. The single-ended models were then extended to differential models.

The penultimate chapter presents a novel VCO design realized in a 0.18 μm CMOS process, featuring a single-turn 8-shape inductor. The implemented VCO shows the oscillation frequency from 4.5 GHz to 5.31 GHz controlled by varactor bias. The calculated FOM is -193.65 dBc/Hz. The entire chip occupies a small area, only 0.6887×1.1538 mm2. The successful inductor design will further advance the design of inductor layouts.

Finally, the application of inductor calibration circuits can help maintain consistent performance for VCO under varying environmental conditions, enhancing system reliability and signal quality. Expanding on the lumped circuit model of the 8-shape inductor discussed in previous chapters, as well as the VCO design implemented using a single-turn 8-shape inductor in a 0.18 μm CMOS process, we will incorporate the equivalent model of the 8-shape inductor into its circuit.

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