在半導體奈米量測自動化設備中，光學散射量測儀被視為取代傳統電子顯微鏡擷取微影圖案關鍵尺寸的重要技術，光學散射量測法的優點包含：量測速度快約為現有電子顯微鏡的三倍，可重複性量測同一微影圖案之關鍵尺寸，而且選擇適當的量測波長不會對形成圖案的光阻產生影響，以及提供三維圖形的資訊。現有光學散射量測儀所採取的計算方式為使用嚴格耦合波演算法來預測關鍵尺寸的大小，這是由於此演算結構易於植入計算機系統並且演算速度快，然而此種演算法瓶頸是無法針對微影圖案位於製程疊層中含有非等向性或是金屬材料層以及孤立線圖案做準確的關鍵尺寸估測。本論文針對最新製程的高介電層金屬閘製程疊層等效於繞射光柵結構分析，探討半導體疊層上線微影圖案的不同週期、製程疊層對於繞射效率敏感度、不同三維參數對於繞射效率影響，且比較使用有限時域差分法與嚴格耦合波理論兩種數值方法所計算的零階與正負壹階繞射效率差異。本論文結論可以做為使用有限時域差分法替代嚴格耦合波演算法之參考依據。

Metrology has been the key to ensure the reliability of high volume manufacturing processes in the semiconductor foundry, including the measurements of the critical dimension (CD), the film thickness, the overlay, the wafer geometry, the surface profiling, and the resistivity. The optical scatterometry instrument is attracting more attention to measure the three dimensional shapes of features on integrated circuits (IC) due to its rapid measurement speed, better repeatability measurement, non-destructive measurement, and complete pattern profile information as compared with the conventional CD-SEM (Critical Dimension Scanning Electron Microscope) tool. The rigorous couple wave analysis (RCWA) technique is currently the most popular algorithm implemented in the optical scatterometry to reconstruct CDs of lithography patterns with the prediction limit for the process stacks containing the anisotropic or the metal layers. In order to solve the issues, this study uses finite difference time domain (FDTD) method as an alternative to RCWA for the CD estimation of the patterns on the stacks with the metal layers. The development steps start from the theoretical calculation of the diffraction response from the high-k metal gate (HKMG) process stacks as one-dimensional optical gratings. The diffraction efficiency of the 0th and 1st order is compared between RCWA and FDTD methods. The numerical results based on the FDTD method to retrieve the sensitivity parameters including the CD, the side wall angle, and the height.

[1]Peter Clarke, "Taiwan Now The World's Leading Chip Maker," News and Analysis, EE Times, 2012.
[2]DIGITIMES電子時報, http://digitimes.com.tw/.
[3]Paolo-gargini, Intel Nanotechnology Overview, pp.44-45, 2010.
[4]李冠樺，「ITRS技術藍圖大幅修訂 半導體製程技術再躍進」，新電子234期9月號，2005。
[5]Stephen Y. Chou, Peter R. Krauss, and Preston J. Renstrom, "Imprint of Sub-25nm Vias and Trenches in Polymers," Applied Physics Letters, vol. 67, no. 20, pp. 3114-3116, 1995.
[6]Victor M. Martinez and Thomas F. Edgar, "Control of Lithography in Semiconductor Manufacturing," Control Systems, IEEE, vol. 26, Issue 6, pp. 46-55, 2006.
[7]R. Fabian Pease and Stephen Y. Chou, "Lithography and Other Patterning Techniques for Future Electronics," Proceedings of the IEEE, vol. 96, Issue 2, pp. 248-270, 2008.
[8]Jack J.H. Chen, Faruk Krecinic, Jen-Hom Chen, Raymond P.S. Chen, and Burn J. Lin, "Future Electron-Beam Lithography and Implications on Design and CAD Tools," Design Automation Conference, 2011 16th Asia and South Pacific, pp. 403-404, 2011.
[9]Vivek Singh, "Lithography at 14nm and Beyond: Choices and Challenges," Design Automation Conference, 2011 48th ACM/EDAC/IEEE, pp. 459, 2011.
[10]Lloyd R. Harriott, "Limits of Lithography," Proceedings of the IEEE, vol. 89, Issue 3, pp. 366-374, 2001.
[11]David Z. Pan, Jae-seok Yang, Kun Yuan, Minsik Cho, and Yongchan Ban, "Layout Optimizations for Double Patterning Lithography," ASIC, 2009 IEEE 8th International Conference on, pp. 726-729, 2009.
[12]A.J. Strowjas, T. Jhaveri, V. Rovner, L. Pileggi, "Creating an Affordable 22nm Node Using Design-Lithography Co-Optimization," Design Automation Conference, 2009 46th ACM/IEEE, pp. 95-96, 2009.
[13]David Z. Pan, Jae-Seok Yang, Kun Yuan, and Minsik Cho, "CAD for Double Patterning Lithography," IC Design and Technology, 2010 IEEE International Conference on, pp. 122-125, 2010.
[14]Kurt Ronse, Philippe Jansen, R. Gronheid, Eric Hendrickx, M. Maenhoudt, Vincent Wiaux, Anne-Marie Goethals, R. Jonckheere, and G. Vandenberghe, "Lithography Options for the 32 nm Half Pitch Node and Beyond," IEEE Transactions on Circuits and Systems, vol. 56, no. 8, pp. 1883-1890, 2009.
[15]International Technology Roadmap., Edition Executive Summary, 2009.
[16]Masatoshi Kotera, Kei Yagura, Takeshi Maekawa, Daichi Kawano and Hiroyuki Tanaka, "Photoelectron Trajectory Simulation in a Resist for EUV Lithography," Microprocesses and Nanotechnology, 2007 Digest of papers, pp. 94-95, 2007.
[17]Y. Teramoto, Z. Narihiro, D. Yamatani, T. Yokoyama, K. Bessho, Y. Joshima, T. Shirai, S. Mouri, T. Inoue, H. Mizokoshi, H. Yabuta, K.C. Paul, T. Takemura, T. Yokota, K. Kabuki, K. Miyauchi, K. Hotta, H. Sato, G. Niimi, T. Hosokai, "Tin-Fueled High-Repetition-Rate Z-pinch EUV Source for Semiconductor Lithography," Plasma Science, 2007 IEEE 34th International Conference on, pp. 611, 2007.
[18]Takashi Kamo, Hajime Aoyama, Toshihiko Tanaka, and Osamu Suga, "Effects of Mask Absorber Thickness on Printability in EUV Lithography with High Resolution Resist," Mask and Lithography Conference, 2009 25th European, pp. 1-12, 2009.
[19]Stefan Wurm, "Transition to EUV Lithography," VLSI Technology, Systems, and Applications, 2012 International Symposium on, pp. 1-2, 2012.
[20]N. Nakamura, Y. Takigawa, E. Soda, N. Hosoi, Y. Tarumi, H. Aoyama, Y. Tanaka, D. Kawamura, S. Ogawa, N. Oda, S. Kondo, I. Mori, and S. Saito, "Design Impact Study of Wiring Size and Barrier Metal on Device Performance toward 22 nm-node Featuring EUV Lithography," Interconnect Technology Conference, 2009 IEEE International, pp. 14-16, 2009.
[21]C. Mack, Fundamental Principles of Optical Lithography, 2007.
[22]施敏、梅凱瑞、林鴻志，「半導體製程概論」，國立交通大學出版社，新竹， 2008。
[23]Stan Stokowski and Mehdi Vaez-Iravani, "Wafer Inspection Technology Challenges for ULSI Manufacturing," NIST Characterization and Metrology for ULSI Technology, March 1998 International Conference, The American Institute of Physics, 1998.
[24]Unakar NJ, Tsui JY, Harding CV, "Scanning Electron Microscopy," Ophthalmic Research 1981, Vol. 13, No. 1, 1981.
[25]Philippe Thony, David Herisson, Daniel Henry, Ermes Severgnini, Mauro Vasconi, "Review of CD Measurement and Scatterometry," characterization and metrology for ULSI technology: 2003 International Conference on Characterization and Metrology for ULSI Technology. AIP Conference Proceedings, Vol. 683, pp. 381-388, 2003.
[26]Hsu-Ting Huang and F.-L. Terry Jr., "Erratum to Spectroscopic Ellipsometry and Reflectometry from Gratings (Scatterometry) for Critical Dimension Measurement and in Situ Real-Time Process Monitoring," Thin Solid Films, vol. 468, pp. 339–346, 2004.
[27]Boher, P., Petit, J., Leroux, T., Foucher, J., Desieres, Y., Hazart, J. and Chaton, P., "Optical Fourier Transform Scatterometry for LER and LWR Metrology," Proc. SPIE, vol. 5752, pp. 192-203, 2005.
[28]Brent C. Bergner, Thomas A. Germer and Thomas J. Suleski, "Effect of Line Width Roughness on Optical Scatterometry Measurements," Proc. of SPIE, Vol. 7272, pp. 72720U1-8, 2009.
[29]K. P. Bishop, S. M. Gaspar, L. M. Milner, S. Sohail, H. Naqvi and J. R. McNeil, "Grating Line Shape Characterization Using Scatterometry," Proc. SPIE, vol. 1545, pp. 64, 1991.
[30]J. Opsal, H. Chu, Y. Wen, Y. C. Chang and G. Li, "Fundamental Solution for Real-Time Optical CD Metrology," in Metrology, Inspection, and Process Control for Microlithography XVI, D. J. Herr, ed., Proc. SPIE, vol. 4689, pp. 163-176, 2002.
[31]W. D. Mieher, T. G. Dziura, X. Chen, P. DeCecco, A. Levy,"Spectroscopic CD Metrology for Sub 100nm Lithography Process Control," Metrology, Inspection and Process Control for Microlithography, Proc. SPIE, vol. 4689, pp. 957, 2002.
[32]V. Machavariani, S. Gov, Y. Cohen, "Scatterometry: Interpretation by Different Methods of Electromagnetic Simulation," Proc. SPIE, vol. 4689, pp. 177-188, 2002.
[33]J. M. Holden, T. Gubiotti, W. A. McGaham, M. Dusab, and T. Kiersb,"Normal Incidence Spectroscopic Ellipsometry and Polarized Reflectometry for Measurement of Photoresist Critical Dimensions," Proc. SPIE, vol. 4989, pp. 1110–1121, 2002.
[34]John C. Lam, Alexander Gray, Stanley Chen, and Jan Richter, "Measuring Contact Hole Corner RoundingUniformity Using Optical Scatterometry," Mask and Lithography Conference, 2008 24th European, pp. 1-4, 2008.
[35]F. Flach, S. Volkland, G. Holfeld, J. Schneider, and T. Schade, "Fast and Efficient Characterization of Photolithographic Systems by Optical Scatterometry," Semiconductor Conference Dresden, pp. 1-3, 2011.
[36]P.C. Logofatu, D. Apostol, V. Damian, V. Nascov, F. Garoi, A. Timcu, I. Iordache, "Scatterometry, an Optical Metrology Technique for Lithography," Semiconductor Conference, 2004 International, vol. 2, pp. 517-520, 2004.
[37]Szymon Lis, Jaroslaw Mysliwiec, Andrzej Miniewicz, and Sergiusz Patela, "Characterization of Two Dimensional Photonics Structures using Optical Sccaterometry," Photonics and Microsystems, 2008 International Students and Young Scientists Workshop, pp. 39-42, 2008.
[38]Bartlomiej Salski, Malgorzata Celuch, and Wojciech Gwarek, "FDTD Modeling of Finite Spot Scatterometry," Microwaves, Radar and Wireless Communications, 2008 17th International Conference on, pp. 1-4, 2008.
[39]T. K. Gaylord and M. G. Moharam, "Planar Dielectric Grating Diffraction Theories," Applied Physics B: Lasers and Optics, vol. 28, pp. 1-14, 1982.
[40]Lifeng Li, "A Modal Analysis of Lamellar Diffraction Gratings in Conical Mountings," Journal Of Modern Optics, vol. 40, no. 4, pp. 553-573, 1993.
[41]N. Chateau and J.-P. Hugonin, "Algorithm for The Rigorous Coupled-Wave Analysis of Grating Diffraction," Journal of the Optical Society of America A, vol. 11, no. 4, 1994.
[42]D. M. Pai and K. A. Awada, "Analysis of Dielectric Gratings of Arbitrary Profiles and Thicknesses," Journal of the Optical Society of America A, vol. 8, no. 5, 1991.
[43]Partha P. Banerjee and John M. Jarem, "Convergence of Electromagnetic Field Components Across Discontinuous Permittivity Profiles," Journal of the Optical Society of America A, vol. 17, no. 3, 2000.
[44]Lifeng Li and Charles W. Haggans, "Convergence of The Coupled-Wave Method for Metallic Lamellar Diffraction Gratings," Journal of the Optical Society of America A, vol. 10, no. 6, 1993.
[45]Philippe Lalanne, "Convergence Performance of The Coupled-Wave and The Differential Methods for Thin Gratings," Journal of the Optical Society of America A, vol. 14, no. 7, 1997.
[46]E. Popov and M. Neviere, "Differential Theory for Diffraction Gratings: a New Formulation for TM Polarization With Rapid Convergence," Optics Letters, vol. 25, no. 9, 2000.
[47]S. Peng and G. M. Morris, "Efficient Implementation of Rigorous Coupled-Wave Analysis for Surface-Relief Gratings," Journal of the Optical Society of America A, vol. 12, no. 5, 1995.
[48]G. Granet and B. Guizal, "Efficient Implementation of The Coupled-Wave Method for Metallic Lamellar Gratings in TM Polarization," Journal of the Optical Society of America A, vol. 13, no. 5, 1996.
[49]Soon Ting Han, Yuh-Luen Tsao, Rodger M. Walser, and Michael F. Becker, "Electromagnetic Scattering of Two-Dimensional Surface-Relief Dielectric Gratings," Applied Optics, vol. 31, no. 13, 1992.
[50]M. G. Moharam, Eric B. Grann, Drew A. Pommet, and T. K. Gaylord, "Formulation for Stable and Efficient Implementation of The Rigorous Coupled-Wave Analysis of Binary Gratings," Journal of the Optical Society of America A, vol. 12, no. 5, 1995.
[51]E. Popov and M. Neviere, "Grating Theory: New Equations in Fourier Space Leading to Fast Converging Results for TM Polarization," Journal of the Optical Society of America A, vol. 17, no. 10, 2000.
[52]Hirokimi Shirasaki, "3D Semiconductor Grooves Measurement Simulations (Scatterometry) using Nonstandard FDTD Methods," Proc. of SPIE, vol. 6922, pp. 69223T, 2008.
[53]Hirokimi Shirasaki, "3D Anisotropic Semiconductor Grooves Measurement Simulations (Scatterometry) using FDTD Methods," Proc. of SPIE, vol. 6518, pp. 65184D, 2007.
[54]Hirokimi Shirasaki, "Arbitrary 3D Linewidth form Measurement Simulations for the Next-Generation Semiconductor Circuits by Scatterometry using the FDTD Method," Proc. of SPIE, vol. 5375, pp. 1339-1345, 2004.
[55]Hirokimi Shirasaki, "3D Isolated and Periodic Grooves Measurement Simulations for the Semiconductor Circuits by Scatterometry Using the FDTD Methods and the Time Shortening Calculation Method," Proc. of SPIE, vol. 6152, pp. 61523O, 2006.
[56]Hirokimi Shirasaki, "Arbitrary Cross Sections and Stack Forms Measurement Simulations for the Semiconductor Circuits by Scatterometry," Proc. of SPIE, vol. 5752, pp. 790-797, 2005.
[57]J.-A. Kim, S.-J. Kim, S.-B. Chin, S.-H. Oh, D. Goo, S.-J. Lee, S.-G. Woo, H.-K. Cho, W.-S. Han, J.-T. Moon, C. J. Raymond and M. E. Littau, "Successful Application of Angular Scatterometry to Process Control in Sub-100-nm DRAM," Proc. SPIE, vol. 5375, pp. 541-549, 2004.
[58]T. Hingst, M. Moert, P. Reing, E. Backen, R. Dost, P. Weidner, J. Hopkins, T. G. Dziura, A. Elazami and R. Freed, "Spectroscopic Ellipsometry-Based Scatterometry for Depth and Linewidth Measurements of Polysilicon-Filled Deep Trenches," Proc. SPIE, vol. 5375, pp. 587-596, 2004.
[59]R. C.-J. Chen, F.-C. Chen, Y.-Y. Luo, B.-C.Perng, Y.-H. Chiu and H.-J. Tao, "Application of Spectroscopic Ellipsometry-Based Scatterometry for Ultrathin Spacer Structure," Proc. SPIE, vol. 5375, pp. 1374-1382, 2004.
[60]D. Herisson, D. Neira, C. Fernand, P. Thony, D. Henry, S. Kremer, M. Polli, M. Guevremont and A. Elazami, "Spectroscopic Ellipsometry for Lithography Front-End Level CD Control: a Complete Analysis for Production Integration," Proc. SPIE, vol. 5038, pp. 264-273, 2003.
[61]J. Bishoff, R. Brunner, J. Bauer and U. Haak, "Light Diffraction Based Overlay Measurement," Metrology, Proc. SPIE, vol. 4344, pp. 222-233, 2001.
[62]顧逸霞，「散射儀於半導體製程檢測之應用」，半導體科技No.52，2005。
[63]張玉姍、楊富翔、吳智誠、羅偕益，「提升顯示器出貨品質　FPD膜層檢測技術扮要角」，FPD產業檢測標準與實務專欄，2007。
[64]Lifeng Li, "Multilayer Modal Method for Diffraction Gratings of Arbitrary Profile, Depth, and Permittivity," Journal of the Optical Society of America A, Vol. 10, Issue 12, pp. 2581-2591, 1993.
[65]Moharam, M. G., Gaylord, T. K., "Rigorous Coupled-Wave Analysis of Planar-Grating Diffraction," Journal of the Optical Society of America, vol. 71, issue 7, pp.811, 1981.
[66]Nicolas Chateau, Jean-Paul Hugonin, "Algorithm for the Rigorous Coupled-Wave Analysis of Grating Diffraction," Journal of the Optical Society of America A, Vol. 11, Issue 4, pp. 1321-1331, 1994.
[67]M. G. Moharam, T. K. Gaylord, "Rigorous Coupled-Wave Analysis of Metallic Surface-Relief Gratings," Journal of the Optical Society of America A, Vol. 3, Issue 11, pp. 1780-1787, 1986.
[68]P. Lalanne and G. M. Morris, "Highly Improved Convergence of the Coupled-Wave Method for TM Polarization," Journal of the Optical Society of America A, vol. 13, no. 4, 1996.
[69]Philippe Lalanne, "Improved Formulation of the Coupled-Wave Method for Two-Dimensional Gratings," Journal of the Optical Society of America A, vol. 14, no. 7, 1997.
[70]Gang Bao, David C. Dobson, and J. Allen Cox, "Mathematical Studies in Rigorous Grating Theory," Journal of the Optical Society of America A, vol. 12, no. 5, 1995.
[71]E. Popov and M. Neviere, "Maxwell Equations in Fourier Space: Fast-Converging Formulation for Diffraction by Arbitrary Shaped, Periodic, Anisotropic Media," Journal of the Optical Society of America A, vol. 18, no. 11, 2001.
[72]Lifeng Li, "New Formulation of the Fourier Modal Method for Crossed Surface-Relief Gratings," Journal of the Optical Society of America A, vol. 14, no. 10, 1997.
[73]M. G. Moharam, Drew A. Pommet, Eric B. Grann, and T. K. Gaylord, "Stable Implementation of the Rigorous Coupled-Wave Analysis for Surface-Relief Gratings: Enhanced Transmittance Matrix Approach," Journal of the Optical Society of America A, vol. 12, no. 5, 1995.
[74]Evgeny Popov, Michel Neviere, Boris Gralak, and Gerard Tayeb, "Staircase Approximation Validity for Arbitrary-Shaped Gratings," Journal of the Optical Society of America A, vol. 19, no. 1, 2002.
[75]Lifeng Li, "Use of Fourier Series in the Analysis of Discontinuous Periodic Structures," Journal of the Optical Society of America A, vol. 13, no. 9, 1996.
[76]Atef Z. Elsherbeni and Veysel Demir, The Finite Difference Time Domain Method for Electromagnetics with MATLAB Simulations, SciTech Publishing, Raleigh, NC, 2009.
[77]K. S. Yee, "Numerical Solution of Initial Boundary Value Problems Involving Maxwell's Equations in Isotropic Media," IEEE Transactions on Antennas and Propagation, vol. 14, pp. 302-307, 1966.
[78]李長綱，電磁學與電磁波的理論及應用(下)，鼎茂圖書出版股份有限公司，台北，2010。
[79]欒丕綱、陳啟昌，光子晶體，五南圖書出版公司，台北，2010.
[80]宋健民，「先進半導體製程與材料選擇」，半導體科技，2008。
[81]Y. Nara, F. Ootsuka, S. Inumiya, and Y. Ohji, "High-k/Metal Gate Stack Technology for Advanced CMOS," Solid-State and Integrated Circuit Technology, 8th International Conference on, pp. 360-363, 2006.
[82]K. Mistry, C. Allen, C. Auth, B. Beattie, D. Bergstrom, M. Bost, M. Brazier, M. Buehler, A. Cappellani, R. Chau, C.-H. Choi, G. Ding, K. Fischer, T. Ghani, R. Grover, W. Han, D. Hanken, M. Hattendorf, J. He, J. Hicks, R. Huessner, D. Ingerly, P. Jain, R. James, L. Jong, S. Joshi, C. Kenyon, K. Kuhn, K. Lee, H. Liu, J. Maiz, B. McIntyre, P. Moon, J. Neirynck, S. Pae, C. Parker, D. Parsons, C. Prasad, L. Pipes, M. Prince, P. Ranade, T. Reynolds, J. Sandford, L. Shifren, J. Sebastian, J. Seiple, D. Simon, S. Sivakumar, P. Smith, C. Thomas, T. Troeger, P. Vandervoorn, S. Williams, K. Zawadzki, "A 45nm Logic Technology with High-k+Metal Gate Transistors, Strained Silicon, 9 Cu Interconnect Layers, 193nm Dry Patterning, and 100% Pb-free Packaging," Electron Devices Meeting of 2007 IEEE International, pp. 247-250, 2007.
[83]S. Natarajan, M. Armstrong, M. Bost, R. Brain, M. Brazier, C-H Chang, V. Chikarmane, M. Childs, H. Deshpande, K. Dev, G. Ding, T. Ghani, O. Golonzka, W. Han, J. He, R. Heussner, R. James, I. Jin, C. Kenyon, S. Klopcic, S-H. Lee, M. Liu, S. Lodha, B. McFadden, A. Murthy, L. Neiberg, J. Neirynck, P. Packan, S. Pae, C. Parker, C. Pelto, L. Pipes, J. Sebastian, J. Seiple, B. Sell, S. Sivakumar, B. Song, K. Tone, T. Troeger, C. Weber, M. Yang, A. Yeoh, K. Zhang, "A 32nm Logic Technology Featuring 2nd-Generation High-k + Metal-Gate Transistors, Enhanced Channel Strain and 0.171µm2 SRAM Cell Size in a 291Mb Array," Electron Devices Meeting of 2008 IEEE International, pp. 1-3, 2008.
[84]C. Auth, A. Cappellani, J.-S. Chun, A. Dalis, A. Davis, T. Ghani, G. Glass, T. Glassman, M. Harper, M. Hattendorf, P. Hentges, S. Jaloviar, S. Joshi, J. Klaus, K. Kuhn, D. Lavric, M. Lu, H. Mariappan, K. Mistry, B. Norris, N. Rahhal-orabi, P. Ranade, J. Sandford, L. Shifren, V. Souw, K. Tone, F. Tambwe, A. Thompson, D. Towner, T. Troeger, P. Vandervoorn, C. Wallace, J. Wiedemer, C. Wiegand, "45nm High-k + Metal Gate Strain-Enhanced Transistors," VLSI Technology, 2008 Symposium on, pp. 128-129, 2008.
[85]Harold Pilo, Igor Arsovsi, Kevin Batson, Geordie Braceras, John Gabric, Robert Houle, Steve Lamphier, Carl Radens, and Adnan Seferagic, "A 64 Mb SRAM in 32 nm High-k Metal-Gate SOI Technology With 0.7 V Operation Enabled by Stability, Write-Ability and Read-Ability Enhancements," IEEE Journal of Solid-State Circuits, vol. 47, no. 1, 2012.
[86]Chang Yong Kang, Rino Choi, S. C. Song, and B. H. Lee, "Effects of Gate Edge Profile on Off-State Leakage Suppresion in Metal Gate/High-k Dielectric N-Type Metal-Oxide-Semiconductor Field Effect Transistors," Applied Physics Letters, vol. 90, pp. 183501, 2007.
[87]Yee-Chia Yeo, Pushkar Ranade, Tsu-Jae King, and Chenming Hu, "Effects of High-k Gate Dielectric Materials on Metal and Silicon Gate Workfunctions," IEEE Electron Device Letters, vol. 23, no. 6, 2002.
[88]Sanghun Jeon, Jeong Hee Han, Jung Hoon Lee, Sangmoo Choi, Hyunsang Hwang, and Chungwoo Kim, "High Work-Function Metal Gate and High-k Dielectrics for Charge Trap Flash Memory Device Applications," IEEE Transactions on Electron Devices, vol. 52, no. 12, 2005.
[89]Vaid, A., Sendelbach, M., Komarov, S., Dziura, T., Ferns, J., Madsen, J., "Improved Scatterometry Time to Solution for Leading-Edge Logic Applications," 2010 IEEE/SEMI Advanced Semiconductor Manufacturing Conference (ASMC), San Francisco, CA, 2010.
[90]Huang, Yu-Hao, Chen, Howard, Shen, Kyle, Chen, H. H., Yu, Chun Chi, Liao, J. H., Zhang, Xiafang, Teo, Russell, Xu, Zhi-Qing, Yoo, Sungchul, Lin, Ching-Hung, Cheng, Chao-Yu, Lin, Jason, "Scatterometry Measurement for Gate ADI and AEI Critical Dimension of 28nm Metal Gate Technology," Proceedings of the SPIE, Volume 7971, pp. 79712O-79712O-9, 2011.
[91]Dziura, Thaddeus G., Bunday, Benjamin, Smith, Casey, Hussain, Muhammad M., Harris, Rusty, Zhang, Xiafang, Price, Jimmy M., "Measurement of High-k and Metal Film Thickness on FinFET Sidewalls using Scatterometry," Proceedings of the SPIE, Volume 6922, pp. 69220V-69220V-8, 2008.
[92]Wen-Kuan Yeh, Yu-Ting Chen, Fon-Shan Huang, Chia-Wei Hsu, Chun-Yu Chen, Yean-Kuen Fang, Kwang-Jow Gan, Po-Ying Chen,"The Improvement of High-k/Metal Gate pMOSFET Performance and Reliability Using Optimized Si Cap/SiGe Channel Structure," IEEE Transactions on Device and Materials Reliability, vol. 11, pp. 7-12, 2011.